Termination of Clock Distribution Devices for High-Speed ​​Converters

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Figure 1. ADCLK925 RMS jitter vs. input slew rate.

The ADCLK9542 clock fanout buffer and the ADCLK9143 ultrafast clock buffer are two such clock distribution devices. The ADCLK954 includes 12 output drivers that can drive a full 800-mV swing of ECL (emitter coupled logic) or LVPECL (low voltage positive ECL) signal into a 50-Ω load, resulting in a total differential output swing of 1.6 V, as shown in Figure 2. It can operate at a 4.8 GHz toggle rate. The ADCLK914 can drive a 1.9 V high voltage differential signal (HVDS) into a 50-Ω load, resulting in a total differential output swing of 3.8 V. The ADCLK914 has a 7.5-GHz toggle rate. This article is from Electronics Enthusiasts Network ( http://www.elecfans.com)

When driving a DAC, the clock distribution device should be placed as close as possible to the DAC's clock input so that the required high slew rate, high amplitude clock signal does not cause routing difficulties, generate EMI, or be attenuated by dielectric and other losses. It is worth noting that the characteristic impedance (Z0) of the trace varies with the trace dimensions (length, width, and depth); the output impedance of the driver must match the characteristic impedance.

Figure 2. Output waveform of the ADCLK954 clock buffer when powered by a 3.3V supply.

Output Termination

Clock signal attenuation increases jitter, so it is important to terminate the driver output to avoid signal reflections and achieve maximum energy transfer over a relatively large bandwidth. Indeed, reflections can cause undershoot and overshoot, severely degrading the signal and overall clock performance, or in extreme cases, possibly damaging the receiver or driver. Reflections are caused by impedance mismatches and occur when traces are not properly terminated. This is more important for high-speed signals with fast rise and fall times, as the reflection coefficient itself has a high-pass characteristic. The reflected pulse is superimposed on the main clock signal, weakening the clock pulse. As shown in Figure 3, it adds uncertain delay or jitter to the rising and falling edges, affecting the edges of the clock signal.

Figure 3. Reflected signal jitter caused by improper termination.

Improper termination makes the amplitude of the echo vary with time, so ∆t also varies with time. The time constant of the termination also affects the shape and width of the echo pulse. For the above reasons, the additional jitter caused by reflections looks like the Gaussian characteristic of adding classical jitter. To avoid the adverse effects of jitter and clock quality degradation, proper signal termination methods summarized in Table 1 are required. Z0 is the impedance of the transmission line; ZOUT is the output impedance of the driver and ZIN is the input impedance of the receiver. Only CMOS and PECL/LVPECL circuits are shown.

Table 1. Clock Termination

Method Description Strengths Weaknesses Remarks

Serial Terminated CMOS