LED large screen system design based on Cyclone EP1C6 and SPCE061A

The control circuits of the LED large-screen display systems currently used are mostly composed of a single or multiple single-chip microcomputers and complex peripheral circuits. The single-chip microcomputer programming is relatively complex, the debugging of the entire circuit is relatively troublesome, and the reliability and real-time performance are difficult to guarantee. In view of this situation, this paper proposes a LED large-screen solution based on SPCE061A and Cyclone EP1C6. This design does not require external FLASH ROM and RAM, and does not require any external functional circuits. All functions are realized by one EP1C6 and one SPCE061A, with fast data processing speed and high reliability.

Introduction to SPCE061A and Cyclone EP1C6

SPCE061A is a 16-bit microcontroller from Lingyang Technology, with 32KB flash memory and 2KB word SRAM embedded. The CPU can work at a maximum frequency of 49MHz. The high processing speed enables SPCE061A to process complex digital signals very easily and quickly. This article designs a monochrome (red) display screen with a dot matrix size of 192×128, and displays 5 screens of data continuously as required. The rich on-chip resources of SPCE061A just meet such large data processing and storage requirements. This article adopts the method of receiving host computer data by UART interrupt and writing the data into 32KB flash memory, replacing the traditional MCU+ROM+RAM design, which increases the stability of the system.

Cyclone EP1C6 is a cost-effective FPGA launched by Altera. The device provides an asynchronous, dual-port memory module with a register input port and an optional register output port. The M4K is set as a dual-port RAM in this design to achieve data read and write synchronization and improve the system refresh frequency.

Overall design solution

This system is designed to be an electronic large screen with 192×128 red LED dot matrix. The entire large screen is a modular structure, with 4 16×16 dot matrix blocks as a minimum module, and each row of dot matrix is ​​cascaded by 3 identical minimum modules, with a total of 8 rows. The large screen is required to display 5 screens of content continuously, and each screen has animation effects such as up, down, left, and right movement. In actual applications, the main control room is about 200 meters away from the electronic screen. Combining the requirements of the design object and the characteristics of large-screen design, this paper proposes a novel design scheme. The overall block diagram of the scheme is shown in Figure 1.

The LED large screen system consists of three main units: the host computer image/text editing and sending unit, the main control board unit, and the display drive circuit unit. The system host computer is controlled by a PC, which mainly edits and sends image/text information to the memory of the main control board; the main control board processes these font data and sends them to the large screen, and displays them on the large screen.

System hardware design

The information sent by the host computer is transmitted to the main control board through the twisted pair cable via the interface that meets the RS-422 standard. The communication rate can be set in the host computer software. The chips used in the interface are MC3487 and MC3486. When the transmission rate of RS-422 is 100kb/s, the maximum transmission distance is 1200 meters. The transmission distance of this system is about 200 meters, and the maximum transmission rate is 115kb/s. The use of RS-422 transmission can meet the requirements of this long-distance communication.

Main control board unit design

The design feature of this unit is the monolithic integration of data stream reception, storage and drive scanning, without any peripheral circuits. The main control board consists of a SPCE061A and EP1C6, as shown in Figure 2.

The design idea of ​​this unit is that the IOB7 port of the single-chip microcomputer receives the data sent by the host computer in the form of UART interrupt. This is because the large screen is in a passive, cyclic display state. The use of asynchronous transmission can reduce the system consumption of the system constantly querying the serial port receiving flag. The single-chip microcomputer writes the received serial port data into the built-in flash memory one by one in units of two bytes. The 2KB SRAM inside the single-chip microcomputer is used as a cache area. Whenever the single-chip microcomputer wants to write a new screen of data to the FPGA, it first reads the data from the flash memory according to a specific address and stores it in the SRAM, and then writes the data in the SRAM in parallel to the dual-port RAM of the FGGA. In addition to 16 data lines, the interface signal between the single-chip microcomputer and the FPGA also includes the address, write enable and write clock of the single-chip microcomputer writing data to the FPGA. Since the number of dots per screen is 192×128, 11 address lines are required for parallel transmission of 16-bit data. However, due to design requirements, an additional address line is specially set up in the system to read and write partitions for the dual-port RAM of the FPGA, so a total of 12 address lines are used.

FPGA configures a dual-port RAM inside to cache the data written by the microcontroller, and selectively reads out the data according to the structure of the large screen and the characteristics of the scanning circuit, and then outputs the data from parallel to serial to the scanning drive circuit of the large screen. Since the large screen adopts a modular interlaced scanning method, each row requires 2 data lines for interlaced transmission, and the entire large screen requires a total of 16 data lines. Since the row and column drivers of the dot matrix are all driven by 74LS595, the FPGA should also generate the dot clock and latch signals for column scanning and the data, clock, and latch signals for row scanning.

Dual-port RAM configuration

Since data display is a dynamic scanning method, if a RAM area is used, when the microcontroller writes to the RAM, the FPGA can only be in a waiting state, which will cause the dynamic scanning of the screen to stop. Since the screen data is shifted and output, when the scanning stops, because a certain row of high level will be maintained for a long time, the row will always maintain a strong brightness, affecting the display effect of the screen. Two RAM areas of the same size are designed in this system: area A and area B, so that the microcontroller can perform write operations alternately. When the microcontroller is writing area A, the FPGA reads the font data in area B; when the microcontroller is writing area B, the FPGA reads the font data in area A. In this way, the FPGA will not stop scanning, ensuring that the dot matrix of each row has the same time duty cycle, so that the screen dot matrix has the same brightness. The HIGHADR pin in the microcontroller can be used to control the write area of ​​the microcontroller and the read area of ​​the FPGA.

Since the size of each screen dot matrix data is 1536 words, the capacity of area A and area B must be at least greater than 1536, so the entire RAM area is at least 1536×2 words. Considering that EP1C6 integrates 20 M4K modules with a capacity of 256 words, it can just meet the RAM requirements of this system. The configuration of dual-port RAM is shown in Figure 3.

Among them, wren is the write enable signal of the microcontroller to write data to the FPGA, wraddress[11..0] is the write address signal, wrclock is the write clock, data[15..0] is the write data, rdaddress[11..0] is the read address signal, rdclock is the clock signal for reading data, and q[15..0] is the read data. For this dual-port RAM, only q[15..0] is the output port, and the others are all input ports. All signals related to writing data are generated by the microcontroller, and all signals for reading data are generated by the FPGA. The highest bit of the read and write address can realize RAM partitioning.

Dot matrix drive circuit

The grayscale of LED in this system is realized by modulating the duty cycle. Since the large screen is a monochrome dot matrix, it is mainly used to display text information, so it requires high and balanced brightness. According to this feature, a modular scanning method of every 8 lines is adopted. Every 8 lines of dot matrix are scanned at the same time, and the duty cycle of each line is 1/8, so that the brightness of the screen is guaranteed.

The driving circuit of the dot matrix is ​​divided into row driving and column driving. The column driving adopts serial data transmission and is easy to modularize. The column driving circuit is composed of 74LS595, and the row driving circuit is composed of 74LS595 and its matching inverter 7406 and PNP Darlington power transistor TIP127. All the data clock signals, data latch signals, scan data, clock, and latch signals of the row driver 74LS595 are together, and all the data clock signals, data latch signals, scan data, clock, and latch signals of the column driver 74LS595 are also together, so that the synchronous display of the large screen can be realized.

Software Design

The system software design consists of three parts: host computer image/text editing and sending software design, microcontroller control unit software design, and FPGA control unit software design.

Host computer software design

The image/text editing and sending software of the host computer is written in Visual Basic. You only need to set the screen size to 192×128 in the interface, select COM1 or COM2 as the serial port, set the baud rate to 9600, set the starting address of each screen and the number of screens to be sent, call in the file containing relevant information, and click the "Send" button. The data flow is transmitted to the main control board through the twisted pair cable that meets the RS-422 standard. The software is suitable for color/monochrome screens of any size and provides rich graphics/text editing and modification functions. You can also directly call the 16-color drawing file (*.bmp) in Windows, so that you can use Windows or various drawing tools based on Windows to design colorful images.

Software Design of Single Chip Microcomputer Control Unit

The software design of the microcontroller control unit mainly implements three major functions: serial data reception, data output, and image display mode conversion. The design process is shown in Figure 4. The serial data reception part mainly receives and saves bitmap files through UART interrupts. The image display mode conversion part realizes image conversion, such as up, down, left, right, etc., to achieve a variety of image display effects.

FPGA control unit software design

The FPGA control unit is developed under the QUARTUSⅡ environment. Its main functions are to configure the dual-port RAM, transmit data and corresponding drive signals to realize the display of serial data. Serial data display is the core of software design. The software design module of this unit is shown in Figure 5.

The configuration of the dual-port RAM is completely implemented by software. Whether the FPGA reads area A or area B of the dual-port RAM is controlled by the HIGHADR pin of the microcontroller. After the FPGA reads the corresponding data according to the requirements of the display driver, it also needs to convert the data from serial to the column driver 74LS595. The scan control signal is generated in the process of sending the data to the display driver, which is used to realize the row and column drive.

Conclusion

The LED large screen solution based on Cyclone EP1C6 and SPCE061A proposed in this paper has been applied on site. Its dual-port RAM and scanning control design based on FPGA make the system stable and reliable. Practice has proved that this system can display text and graphic information of various fonts and models in multiple playback modes. Compared with similar designs, it has clear pictures, stable performance, simple operation and use, and has a good application prospect.