Design of LED large screen display system based on NiosII 32-bit processor

introduction

At present, LED large-screen display systems are divided into two categories according to the data transmission method: one is synchronous real-time display, that is, the content of the computer display system is displayed on the LED video display screen at the same time; the other is asynchronous communication update data display, where the computer transmits data to the independent video source display screen through USB, universal serial interface, Ethernet and other communication methods. Usually, the asynchronous communication control method can only display the screen as a complete area. For display systems with larger screens, sometimes the entire screen needs to be divided into several windows to display different contents respectively, and the content is updated in only one or several windows. In view of this situation, this paper proposes a design scheme based on NiosII32-bit processor, which can effectively realize the display of multiple windows in any position on a single screen, making the display method more flexible and convenient.

1 Overall system design

1.1 System Hardware Structure

The LED display system is mainly composed of a computer system, a data communication transmission module, a data processing module, a scanning control module, a display driver module and an LED screen, as shown in Figure 1. The computer system sends the dot matrix information to be displayed to the storage device through the RS485 serial interface. The data processing module reads the data from the storage device and performs various special display processing, and sends the processed data to the scanning control module. The display driver module receives the data from the scanning control module and sends it to the LED screen for display. The data communication transmission module, data processing module and scanning control module are all implemented on the FPGA, which constitutes an LED asynchronous controller.

1.2 System Software Solution

The software is developed based on NiosIIIDE, and the application is implemented based on μC/OS2II real-time operating system. The software program mainly consists of 2 tasks and 1 timer interrupt service program, and the tasks communicate with each other using semaphores. Task 1 writes the data transmitted from the host computer to the CF card storage device into the memory; Task 2 reads the data from the memory and analyzes and processes it, and sends the analyzed and processed data to the scanning control module. In order to make full use of the real-time and multi-tasking characteristics of μC/OS2II, an embedded file system is used for data management.

2. Design of control system hardware

The data processing module consists of a NiosII soft-core CPU, a SDRAM, and a Flash memory. The NiosII soft-core CPU is the core of the entire controller and is responsible for data processing; the SDRAM is used as a cache when the CPU processes data; the Flash memory is used to store dot matrix information data and LED screen display control parameters.

The scanning control module consists of a user-defined PWM IP core and video memory. The video memory is implemented with a piece of SRAM to store the dot matrix information data of the current display. The PWM module is connected to the NiosIICPU through the Avalon bus, writes the data received from the CPU into the video memory according to the specified address, and then reads the dot matrix information data from the video memory according to a certain addressing method for scanning.

The serial port controller, timer, memory controller, and CF card controller are automatically generated by customizing the integrated IP core using SOPCBuilder software. The hardware structure of this controller is shown in Figure 2.

3. Design of control system software

The control system software is designed based on the real-time operating system μC/OS2II. The operating system uses an efficient task scheduling algorithm to schedule each task, and the display of each window is completed by a single task. The main function creates two tasks: one for reading CF card data; the other for receiving scene data from different display modules and playing display files.

3.1 Data Structure

The storage form of data in the memory directly affects the data access speed and control complexity. This system reorganizes the data in the video memory and the data in the cache, reducing the complexity of data processing and scanning control.

3.1.1 Organization of video memory data

Each pixel of the LED display screen includes three primary colors: red, green, and blue. The grayscale of each color is 256 levels (that is, the grayscale of the pixel is encoded by 8-bit data), so each pixel needs 3 bytes of storage space. When displaying, the red tube, green tube, and blue tube of each pixel are lit at the same time, that is, the data of the three colors are displayed on the screen in parallel.

The data corresponding to the three colors of red, green and blue can be stored separately for easy operation. The data storage method is shown in Figure 3. The data of the same color is stored in a certain area, and the first address of the area is used as the base address of the color. When storing data, each pixel only needs to give a relative change address (displacement), plus the base address of different colors, and the video data of the corresponding point can be found in the three areas.

The grayscale of LED display is realized by weighted scanning. This requires bit separation of color data and then recombining bits with the same weight. For the convenience of operation, each area shown in Figure 3 is further divided into 8 weight areas during storage, and all values ​​with the same weight are concentrated in the corresponding weight area.

The so-called bit separation is to separate the high and low bits of data according to weights and then reorganize them. Bit separation is relatively easy to implement in programmable logic devices. A logic matrix can be divided out, and the data can be stored horizontally and read vertically during operation. The schematic diagram of bit separation is shown in Figure 4.

3.1.2 Organization of cached data

If special effects are to be displayed, there is a certain transformation relationship between the currently displayed data frame and the next data frame. Since the CPU can only write to the video memory, it is necessary to divide a screen area in the cache that is equal in size to the video memory and has a one-to-one corresponding address to store the currently displayed data frame information. If there is overlap between windows, and the special effects data processing operation is performed directly in the screen area, the information of the overlapping parts of the windows may be confused. Therefore, an access space (part1, part2, partn) is divided for each window in the cache to store the previous frame of data information displayed in this window. During the special effects data processing operation, the data information of each window is first processed in the part area, and the converted data is sent to the access space of the corresponding address of each window in the screen area, and finally the data in the screen is written into the video memory corresponding to the address.

3.2 CF card reading software design

Task 1 is responsible for reading the data on the CF card into SDRAM for use by other tasks. A pointer (3pwmdata) is used in the program to allocate space for the data file in SDRAM. When the file system is initialized, the CF card initialization function IDE_initialize() is first called to determine whether the CF card exists. If it exists, the basic information of the file system is read. By calling the function FS_SearchFile (char3FName, FS_TFile3R, unsignedchardir), it is found whether the file to be read exists. If it exists, a buffer is allocated in SDRAM for the data file through the pointer (3pwmdata). When reading, read one sector at a time until all the data is read into SDRAM.

Some program source codes are as follows:

3.3 Overall software design

Based on the above data structure, the software design process is shown in Figure 5. The system first performs initialization operations, then reads the display screen parameters from Flash and initializes the parameters. Then, a task TaskControl() is established, which has a higher priority than each window display task. It is mainly used to manage each window display task in real time. The display of each window is controlled by a single window display task.

The window display task processes the next frame of data in the corresponding part storage area according to the different display modes of each window, and then calls the window display subtask to display it. After completing the display of a frame of data, OSTimeDlyHMSM() is called once to put the current task into a waiting state. The next task with the highest priority and in the ready state is immediately given control of the CPU, thereby completing the switching between window display tasks. Task TaskControl() periodically queries whether Reset is valid. If it is valid, the originally created task is deleted, the number of windows is re-read, a new task is created, and each window display task Task_i is enabled.

The pseudo program segment of the task TaskControl is described as follows:

4 Conclusion

This design makes full use of the high performance of the NiosII 32-bit processor and the efficient task scheduling algorithm of the μC/OS2II real-time operating system to achieve single-screen multi-window display, and the display control becomes more flexible. The entire control system is completed on a single FPGA chip, effectively reducing the cost of the system.