Dynamic Power Management Technology for Multimedia Processors

Multimedia processors are often the most power-hungry devices in portable electronic devices. The common approach to reducing CPU power requirements is to reduce the clock frequency or operating voltage , but this generally results in reduced system performance. On the other hand, chip designers have also come up with various on-chip methods to reduce power consumption without adversely affecting the system. This article introduces what these methods are and how they can be used to achieve power savings, while also discussing some of the external power management devices and power ICs that can help processor chips benefit .

Active Power Management

On-chip power management techniques are applicable to two main types of applications: managing active system power consumption and managing standby power consumption.

Active power management is divided into three parts: dynamic voltage and frequency scaling (DVFS); adaptive voltage scaling (AVS); and dynamic power switching (DPS). Static power management, on the other hand, involves maintaining an idle system in a low-power state until more processing is required. This type of power management uses what is called static leakage management (SLM), which typically utilizes several low-power modes from standby to shutdown.

Let’s look at active mode. With DVFS, clock frequency and voltage are reduced in software based on the performance required by the application. For example, an application processor that includes an advanced RISC machine (ARM) and a digital signal processor (DSP) may not always require all of this computing power, even though the ARM component can run at clock frequencies up to 600 MHz. Typically, software selects several predefined processor operating performance points (OPPs), which include voltages that ensure the processor can run at the lowest frequency that meets the system processing requirements. To gain more flexibility in optimizing power consumption for different application requirements, a separate device core OPP set is predefined for the interconnect and peripherals in the processor.

Corresponding to a given OPP, the software issues control signals to the external regulator to set the minimum voltage. For example, DVFS applies to two voltage sources, VDD1 (powering the DSP and ARM processors) and VDD2 (powering the interconnects between subsystems and peripherals), and these rails provide most of the power required by the chip (typically about 75% to 80% of the total required power). By moving the DSP processor to a low operating performance point where the ARM can run at up to 125MHz clock frequency, while completing MP3 decoding, there is still plenty of power left for other tasks. To achieve this functionality with ideal power consumption, we can reduce VDD1 to 0.95V instead of the maximum voltage of 1.35V that guarantees 600MHz operation.

The second active power management technique, adaptive voltage scaling (AVS), is based on the variations that occur during chip manufacturing and device operating life. This technique is relative to DVFS, where all processors have the same pre-programmed OPP. As one would expect, chip performance at a specified frequency in most existing manufacturing processes fits into a well-defined power distribution. Some devices (i.e., “hot” devices) can achieve the specified frequency at a lower voltage than many “cold” devices. This is where AVS comes into play—the processor detects its own performance level and adjusts the voltage supplies accordingly. Dedicated on-chip AVS hardware implements a feedback loop that does not require processor intervention, dynamically optimizing voltage levels to account for variations in process performance, temperature, and silicon chip performance degradation (see Figure 1).

Figure 1

Figure 1 shows a typical performance distribution for a particular processor. Here, a “cold” device requires 0.94V to run at 125 MHz, while a “hot” device requires only 0.83V to run at the same frequency. Adaptive voltage scaling (AVS) uses a feedback loop that adjusts the supply voltage accordingly so that a single device can run at the frequency required for a particular processing task.

In operation, the software schedules the AVS hardware for each OPP, while the control algorithm sends commands to the external regulators over an I2C bus, incrementally decreasing the output of the corresponding regulator until the processor just exceeds the target frequency requirement.

For example, a developer could start a design targeting 125 MHz at 0.95V at a voltage that fits all (V1 in Figure 1 above). However, if a "hot" device using AVS is inserted into the system, the on-chip feedback mechanism automatically drops the voltage to ARM, 0.85V or lower (V2 in Figure 1 above).

The first two active power management methods achieve the minimum operating voltage required to run parts of the device at the desired speed. In contrast, the third method, dynamic power switching (DPS), determines when the device has completed its current computational task and switches the device to a low-power state if it is not currently needed (see Figure 2). For example, the processor enters a low-power state while waiting for a DMA transfer to complete. When awakened, the processor can quickly return to its normal state within microseconds.

Figure 2

Figure 2 Dynamic power switching (DPS) switches specific parts of a device to a low-power state after completing its task.

Passive Power Management

While DPS can only switch a portion of a multimedia system-on-chip (SoC) to a low-power state, in many cases it makes sense to switch the entire device to a low-power state (either automatically when no applications are running or at the request of the user). To achieve this goal, static leakage management (SLM) can be used, which is used to initiate standby or off mode. A key difference is that in standby mode the device maintains the state of internal memory and logic circuits , while in off mode all system states are stored in external memory. With SLM, wake-up time is much faster than a cold start because the program has already been loaded into external memory and the user does not have to wait for the entire operating system (OS) to restart. A media player might be an example of using SLM: after 10 seconds of no processing and no user input, the media player turns off the display and enters standby or off mode.

For example, TI's OMAP35x single-chip processor devices with an ARM Cortex-A8 core implement a shutdown mode—a lowest power mode from which the device automatically wakes up. All power domains except the wakeup domain are turned off. Thus, power consumption is limited only in the wakeup domain and comes from I/O leakage current . The wakeup domain runs independently at 32 kHz with the system clock turned off. The OMAP35x also automatically sends a signal to the external voltage regulator, which is then turned off in this deep sleep state. No memory or logic circuits in the processor are maintained. Before entering shutdown mode, the system state is saved to external memory; after a wakeup reset, the microprocessor unit (MPU) jumps to the user-defined function and the SDRAM controller configuration is restored from temporary memory.

General Technology

Combining the power management techniques described above , we can handle various operating conditions in an optimal way. When the system activity level of a portable multimedia player is high, such as watching a high-resolution video, an overdrive OPP can be set on VDD1; for web browsing with moderate power requirements, normal OPP can be set for VDD1 and VDD2; listening to music has relatively low power requirements and the lowest OPP can be set for VDD1 and VDD2. In all of these examples, AVS can be activated to reduce the power consumption difference between the "hot" device and the "cold" device. Finally, if the user leaves the media player on and idle for hours or days, SLM can be used to automatically put the device into shutdown mode.

To better understand the energy savings achieved by using these features, consider the following scenarios. Unless otherwise noted, the following examples do not use TI's AVS/SmartReflex technology. In these descriptions, IVA refers to imaging, video, and audio accelerators or subsystems.

Case 1: Shutdown Mode—0.590 mW. This is a minimum power mode from which TI’s OMAP 3 can automatically wake up. In this mode, the entire device is shut down except for the wakeup domain, which runs at less than 32 kHz. The idle regulator is turned off (VDD1 = VDD2 = 0), the SDRAM self-refreshes, and a specific boot sequence restores the SDRAM controller and system state upon wakeup.

Case 2: Standby Mode—7 mW. In this device state, the wakeup domain is operational and all other non-wakeup power domains are in a low-power maintenance state (VDD1 = VDD2 = 0.9V). All logic and memory are maintained. AVS is off.

Case 3: Audio decoding—22 mW (excluding DPLL and IO power consumption). Although the ARM runs at 125 MHz, it only allows DMA to read input data from the multimedia card after it enters sleep mode. The IVA decodes the MP3 frames (44.1 kHz, 128k bps stereo) and sends the decoded data to a buffer located in SDRAM. An on-chip multi-channel buffered serial port sends the data to the audio codec for playback. As for the system configuration, the DSP runs at 90 MHz and goes into a low-power state to save power when cycles are not needed for processing. At this time, VDD1 = 0.9V and VDD2 = 1V.

Case 4: Audio/Video Encoding—540 mW (excluding DPLL and IO power). In this case, audio is captured and encoded (AACe+ at 48 kHz, 32k bps stereo), video is captured and encoded (H.264 VGA resolution at 20 frames/sec, 2.4 Mbsp), and both are stored. At the same time, the video is displayed. In this configuration, the ARM runs at 500 MHz, the DSP runs at 360 MHz, VDD1 = 1.2V, and VDD2 = 1.15V. An on-chip camera subsystem also captures video input from external sensors, a multi-channel buffered serial port captures audio PCM input, the IVA encodes video and audio, the encoded data is stored in the multimedia card, and the display subsystem rotates the video and sends it to the LCD and TV output interfaces.

Implementing Power Management

To achieve extensive flexibility in power management, the DSP processor utilizes an on-chip Power Reset and Clock Manager (PRCM). The OMAP3530 processor divides its functional blocks into 18 power domains, each with its own switches. The PRCM switches all power domains, but many of them are still controlled by the user. In addition, each power domain can be switched to any of four states, depending on whether power is applied to logic and memory, and whether the clock is active or inactive: Active, Inactive, Maintain, or Off.

These states require the use of backup regulators, which are commonly required for some ARM- and DSP-based devices. Many regulators on the market can do this job; of course, these regulators must meet the processor's voltage , current , and power slew rate specifications, while also being able to meet power-up/power-down sequencing requirements. In order to implement DVFS and AVS on ARM- and DSP-based processors, the associated regulators must also have I2C programmability. In shutdown mode, the circuit must be able to switch the VDD1 and VDD2 regulators using I2C commands issued automatically or by dedicated GPIO signals. The second option has a faster wake-up time because it does not have I2C delays. To reduce the burden on the design engineer , it is best to put all the features of these independent functions in a single device, which can greatly reduce the number of components (see Figure 3).

Figure 3

Figure 3 Advanced Voltage Regulator The chip integrates multiple individual switching regulators and low-dropout linear regulators to meet the requirements of the OMAP35x processor to handle various voltage domains.