Design of self-timing circuit based on bit line cyclic charging SRAM mode

In order to combine CRSRAM and dual-mode self-timing circuits more effectively, three major changes were made to the basic structure of CRSRAM. (1) In the traditional CRSRAM structure, the bit line voltage is precharged to VDD before each read operation. This has two disadvantages: first, it adds additional control circuits for read-write operation conversion and circuits for precharging the bit line voltage to different voltages. Second, precharging to VDD adds additional bit line swing. If read and write operations occur alternately, precharging will consume a lot of power. In the circuit structure designed here, both read and write operations start with the same bit line voltage. This will cause the charge and discharge current from the storage cell to the bit line to cause the voltage on the bit line to fluctuate during the read operation , and the charge on the bit line will have an unpredictable loss or increase. Since there is no precharge circuit, the unpredictable change in the charge of the bit line will affect the read and write capabilities of the circuit. However, since the capacitance load of the bit line is large and the drive capability of the storage tube is small, the impact of the read operation on the charge of the bit line will not cause problems with the circuit function. (2) In order to make the control circuit simple, the evaluation mode is placed before the balance mode. In this way, when controlling the timing, it is only necessary to control the time length of the evaluation mode, and the remaining time of the clock cycle is directly used as the time length of the balance mode. Because the balance mode is different from the evaluation mode, an excessively long balance mode time will not increase the extra power consumption. (3) Since the bit line voltage of CRSRAM is a small swing when writing, in order to ensure the correctness of the write operation and increase the write speed, a 7-tube structure memory cell is used to replace the traditional 6-tube cell structure memory cell. The structure of the 7-tube structure memory cell is shown in Figure 2. Its working principle: In each read operation, QE=1 first, the storage data of the storage cell is erased, and then the points of Q0 and Q1 are pulled to the same value. In this way, a small bit line voltage swing can be written smoothly. As shown in Figure 2, the timing control circuit of DMSTCRSRAM includes four parts: a replica array, a dual-mode voltage monitor (DMVD), a timing control unit (TCU) and a QE signal generating circuit (QEG). On the replica column, the original Exchanger is simplified to the case when DIN is all 1, and Q0 of all virtual storage tubes on the replica column is forced to 0 and Q1 is forced to 1. Therefore, in the evaluation mode, the voltage of DBL is pulled up, and the voltage of DBLB is pulled down. Then the logic 0 of Q0 will provide a pull-down current to DBL to slow down its voltage rise, and the logic 1 of Q1 will provide a pull-up current to DBLB to slow down its voltage drop. Therefore, the change process of the bit line voltage in the slowest case is simulated on the virtual bit line, which can ensure that the voltage on the real bit line has reached the voltage value required for operation before the DMVD is triggered. DMVD consists of two comparators with different reference voltages and two transmission tubes controlled by the read and write enable signal WEN. The sense amplifier is used to monitor the voltage difference between DBL and DBLB, and is triggered once the predetermined reference voltage value is reached. The transmission tube load controlled by WEN triggers the corresponding sense amplifier in the read cycle and the write cycle respectively, and its output is input as the signal P to the timing control unit TCU. TCU is essentially an asynchronous level trigger circuit, and its working conditions are as follows: when the CLK rising edge arrives, GTC also rises; and when the P signal rising edge arrives, the GTC signal falls back to a low level. GTCN is the reverse signal of GTC. QE signal generating circuit (QEG), when there is only a rising edge of CLK, due to the effect of the delay unit, the QEN signal is high level, and the pulse width is the delay time. And WEN controls the QEN signal to output the QE signal only when WEN=1 (write cycle). Next, GTC and GTCN can be used to control the entire circuit. Among them, A[i] represents row decoding; A[j] represents column decoding. In the write cycle, CLK rises and is input into TCU, GTC becomes high level, and GTCN becomes low level; then EQ becomes low level, and the balance mode ends. For the bit line selected by the column, EV and WL become high level and enter the evaluation mode. The EV signal in the write cycle also acts on the virtual bit line, causing a voltage difference. When the voltage difference on the virtual bit line reaches a level sufficient to write data, DMVD is triggered to generate a P signal, which is input into the TCU, causing GTC to become low again and GTCN to return to a high level; then, EV and WL become low, EQ returns to a high level, and the circuit changes from evaluation mode to balance mode. In balance mode, the voltages of all bit lines, including the virtual bit line, are charged and discharged back to the initial value. This write operation is over, and the circuit is ready for the next operation. In the read operation, the process is similar. CLK rises and is input into the TCU, GTC becomes high, and GTCN becomes low; then EQ becomes low, and the balance mode ends. The difference is that in the read cycle, the EV signal is always low, so only when WL rises to a high level does it enter the evaluation mode. At this time, the DWL signal also rises to a high level, causing the virtual storage cell to pull down the voltage on DBL. When the voltage on DBL is low enough, DMVD is triggered to generate a P signal, which is input into TCU, causing GTC to become low again and GTCN to return to a high level; subsequently, D-WL and WL become low, EQ returns to a high level, and the circuit changes from evaluation mode to balance mode. In balance mode, the voltages of all bit lines, including the virtual bit lines, are charged and discharged back to their initial values. This read operation is over, and the circuit is ready for the next operation. 3 Conclusion The dual-mode self-timing technology generates different timing signals for the read and write cycles, respectively, and thereby improves the clock cycle and power consumption of the SRAM. The dual-mode self-timing technology takes into account the parasitic capacitance and resistance on the bit line , the different write response times of the storage cell, and the leakage current of the bit line that depends on the stored data. The simulation results show that this dual-mode self-timing technology reduces the clock cycle by 16% to 30.7% and the write power consumption by 15% to 22.7%.