Improve circuit design procedures to improve testability

As miniaturization continues, component and wiring technology has also made great progress, such as highly integrated micro ICs in BGA housings and insulation spacing between conductors reduced to 0.5mm, these are just two examples. The way electronic components are wired has an increasing impact on whether testing can be performed well later in the production process. Here are some important rules and practical tips.

The costs of preparing and implementing production tests can be significantly reduced by following certain procedures (DFT – Design for Testability). These procedures have been developed over the years and, of course, must be expanded and adapted to new production and component technologies. As electronic products become smaller and smaller, two particularly striking problems are now emerging: the number of accessible circuit nodes is decreasing and the application of methods such as in-circuit testing is limited. These problems can be solved by taking appropriate measures in the circuit layout, using new test methods and innovative adapter solutions. Solving the second problem also involves making the test system, which was originally used as a separate process, take on additional tasks. These tasks include programming memory components or implementing integrated component self-tests (Built-in Self Test, BIST) through the test system. Overall, transferring these steps to the test system still creates more added value. In order to successfully implement these measures, corresponding considerations must be made during the product research and development phase.

1. What is testability?

The meaning of testability can be understood as: test engineers can use the simplest method possible to test the characteristics of a component to see if it can meet the expected functions. In simple terms:

l To what extent are the methods for testing whether products meet technical specifications simplified?

How fast can you write a test program?

l To what extent have product failures been discovered?

l To what extent is the method of accessing the test point simplified?

In order to achieve good testability, mechanical and electrical design procedures must be considered. Of course, to achieve the best testability, you need to pay a certain price, but for the entire process, it has a series of benefits and is therefore an important prerequisite for the successful production of the product.

2. Why develop test-friendly technology?

In the past, if a product could not be tested at the previous test point, the problem was simply pushed to the next test point. If a product defect could not be found in production testing, the identification and diagnosis of the defect was simply pushed to functional and system testing.

On the contrary, today people try to find defects as early as possible. The benefit is not only low cost, but more importantly, today's products are very complex, and some manufacturing defects may not be detected at all during functional testing. For example, some components that need to be pre-installed with software or programmed have such problems. (Such as flash memory or ISPs: In-System Programmable Devices) The programming of these components must be planned in the research and development stage, and the test system must also master this programming.

Test-friendly circuit design costs some money, however, test-difficult circuit design costs more. Testing itself has a cost, and the cost of testing increases with the number of test levels; from in-circuit testing to functional testing and system testing, the cost of testing is increasing. If one of the tests is skipped, the cost will be even greater. The general rule is that the cost of each additional level of testing increases by a factor of 10. With test-friendly circuit design, faults can be found early, so that the cost of test-friendly circuit design can be quickly recovered.

3. How does documentation affect testability?

Only by making full use of the complete data in the component development can it be possible to compile a test program that can fully detect faults. In many cases, close cooperation between the development department and the test department is necessary. Documentation has an indisputable influence on the test engineer's understanding of component functions and the development of test strategies. In order to circumvent the problems caused by lack of documentation and poor understanding of component functions, test system manufacturers can rely on software tools that automatically generate test patterns according to random principles, or rely on non-vector methods, which can only be regarded as a stopgap solution.

The complete documentation before testing includes the parts list, circuit design data (mainly CAD data) and detailed information about the function of the service components (such as data sheets). Only with all the information can it be possible to compile test vectors, define component failure patterns or make certain pre-adjustments.

Certain mechanical data are also important, such as those needed to check whether the components are well soldered and positioned. Finally, for programmable components such as flash memories, PLDs, FPGAs, etc., if they are not programmed during final installation but should be programmed on the test system, the respective programming data must also be known. The programming data of flash components should be complete. If the flash chip contains 16Mbit of data, 16Mbit should be available to prevent misunderstandings and avoid address conflicts. This may happen, for example, if a 4Mbit memory is used to provide only 300Kbit of data to a component. Of course, the data should be prepared in a popular standard format, such as Intel's Hex or Motorola's S-record structure. Most test systems can interpret these formats as long as they can program flash or ISP components. Many of the information mentioned above are also necessary for component manufacturing. Of course, a clear distinction should be made between manufacturability and testability, because these are completely different concepts and thus constitute different premises.

4. Good mechanical contact conditions for testability

Even circuits with very good electrical testability can be difficult to test if basic mechanical rules are not followed. Many factors can limit electrical testability. If there are not enough test points or they are too small, the probe bed adapter will have difficulty contacting every node of the circuit. If the test point location and size errors are too large, poor test repeatability will occur. When using a probe bed adapter, you should pay attention to a series of recommendations on the size and positioning of the lock holes and test points.

5. Electrical prerequisites for optimal testability

Electrical preconditions are as important to good testability as mechanical contact conditions. Both are essential. A gate circuit cannot be tested because the start input cannot be contacted through the test point or because the start input is inside the package and cannot be contacted from the outside. In principle, both situations are equally bad and make testing impossible. When designing a circuit, it should be noted that all components to be tested by in-circuit testing methods should have some mechanism to electrically isolate the components. This mechanism can be achieved with the help of the inhibit input, which can control the output of the component in a static high-ohmic state.

Although almost all test systems can backdrive a node to any state, it is best to have a disable input for the node involved, first bring the node to a high-ohm state, and then "smoothly" apply the corresponding level.

Likewise, the clock generator is always disconnected directly from the oscillator via an enable pin, a gate or a plug-in bridge. The enable input must never be connected directly to the circuit, but rather via a 100 ohm resistor . Each component should have its own enable, reset or control pin. It must be avoided that the enable inputs of many components are connected to the circuit using a common resistor. This rule also applies to ASIC components, which should also have a pin via which the output can be brought to a high-ohmic state. It is also very helpful for the tester to initiate a reset if the component can be reset when the operating voltage is applied . In this case, the component can simply be brought to a defined state before testing.

Unused component pins should also be accessible, because undetected shorts in these locations can also cause component failure. In addition, unused gates are often used in design improvements at a later time, and they may be reconnected to the circuit. So it is also important that they should be tested from the beginning to ensure that they are reliable workpieces.

6. Improve testability

Tips for improving testability when using a probe bed adapter

Locking hole

l Diagonal configuration

l Positioning accuracy is ±0.05mm (±2mil)

l Diameter accuracy is ±0.076/-0mm (+3/-0mil)

l Positioning accuracy relative to the test point is ±0.05mm (±2mil)

l The distance from the edge of the component is at least 3mm

l No penetration contact

Test Points

l As square as possible

The test point diameter is at least 0.88mm (35mil)

l Test point size accuracy is ±0.076mm (±3mil)

l The interval accuracy between test points is ±0.076mm (±3mil)

l The test point interval should be 2.5mm as much as possible

l Tin-plated, end surface can be directly welded

l At least 3mm from the edge of the component

All test points should be on the back of the plug-in board if possible

l Test points should be evenly distributed on the plug-in board

Each node has at least one test point (100% channel)

l Spare or unused gates Circuits All have test points

l Power supply Power supply Multiple external test points are distributed in different locations

Component logo

l The logo text is in the same direction

l Model, version, serial number and barcode are clearly marked

l Component names should be clearly visible and placed as close to the components as possible.

7. About flash memory and other programmable components

The programming time of flash memory can sometimes be very long (up to 1 minute for large memories or memory banks). Therefore, reverse driving of other components is not allowed at this time, otherwise the flash memory may be damaged. To avoid this, all components connected to the control lines of the address bus must be placed in a high-ohmic state. Similarly, the data bus must also be able to be placed in an isolated state to ensure that the flash memory is unloaded and can be programmed in the next step.

There are some requirements for In-System Programmable (ISP) components, such as those from companies such as Altera, XilinX and Lattuce, and some other special requirements. In addition to the mechanical and electrical prerequisites for testability, it is also necessary to ensure the possibility of programming and verifying the data. For Altera and Xilinx components, the Serial Vector Format (SVF) is used, which has recently become almost an industry standard. Many test systems can program such components and use the input data in the SVF for the test signal generator. Programming these components via the Boundary-Scan-Kette (JTAG) also programs the serial data format. When compiling the programming data, it is important to take into account the entire chain of components in the circuit and not to restore the data only to the component to be programmed.

During programming, the automatic test signal generator takes into account the entire component chain and connects other components into the bypass model. In contrast, Lattice requires data in JEDEC format and programming in parallel through the usual input and output terminals. After programming, the data is also used to check the component function. The data provided by the development department should be as easy as possible to use directly in the test system or can be applied through simple conversion.

8. What should be paid attention to for boundary scan (JTAG)

Components based on a fine grid of complex components provide test engineers with only a few accessible test points. It is still possible to improve testability. Boundary scan and integrated self-test technologies can be used to shorten test completion time and improve test effectiveness.

For the development engineer and test engineer, a test strategy based on boundary scan and integrated self-test technology is definitely an additional expense. The development engineer must specify the boundary scan components (IEEE-1149.1-standard) used in the circuit and make the corresponding specific test pins accessible (such as test data input-TDI, test data output-TDO, test clock-TCK and test mode select-TMS as well as ggf. test reset). The test engineer creates a boundary scan model for the component (BSDL-Boundary Scan Description Language). At this point, he must know which boundary scan functions and commands the component supports. Boundary scan testing can diagnose short circuits and open circuits down to the pin level. In addition, if the development engineer has specified this, the automatic test of the component can be triggered by the boundary scan command "RunBIST". In particular, when there are many ASICs and other complex components in the circuit, for which there are no conventional test models, the cost of creating the test model can be greatly reduced by using boundary scan components.

The degree of time and cost reduction is different for each component. For a circuit with IC, if 100% discovery is required, about 400,000 test vectors are required. By using boundary scan, the number of test vectors can be reduced to hundreds at the same fault discovery rate. Therefore, the boundary scan method has particular advantages under the condition that there is no test model or the nodes contacting the circuit are limited. Whether to use boundary scan depends on the cost increase in the development and manufacturing process. Boundary scan must be weighed with the time required to discover faults, test time, time to enter the market, and adapter costs, and save as much as possible. In many cases, a mixed solution of traditional online test methods and boundary scan methods is the best solution.