Introduction to the design of 5.0 to 6.5W Ethernet power supply DC/DC converter

This article introduces a Power over Ethernet (PoE) solution using ON Semiconductor's NCP1031 series of monolithic high-voltage switching regulators with internal MOSFETs. This application note details how to build a low-cost, high-efficiency 5.0V DC power supply with an output power of 5.0 to 6.5W (output power depends on the conversion mode - see the DC/DC converter operation principle described below), which also includes the input circuitry associated with responding to the PoE detection and classification protocol. ON Semiconductor can provide a demonstration PCB of the relevant circuit upon user request.

PoE Background Introduction

As the IEEE802.3AF standard, it is now possible to feed power to Ethernet communication devices through Ethernet data transmission lines, as long as the terminal power requirement is less than 13W. The details of DC power transmission and related terminology can be found in this IEEE document. PoE consists of two power entities, namely the power supply equipment (PSE) and the powered device (PD). The PSE typically supplies a nominal 48V DC voltage to the LAN cable, while the PD is a small DC/DC converter at the other end of the cable that converts the 48V to logic levels such as 5.0Vdc or 3.3Vdc for use by the communication circuitry. The PD should be able to operate at a maximum average input power of 12.95W and withstand an input voltage range of 36 to 57Vdc. A specific "protocol" is also required to implement PD detection (signature mode) and classification based on the maximum power level (classification mode).

Signature detection: The upstream PSE device detects the PD by delivering two different voltages in the range of 2.8 to 10Vdc to the PD input. If the PD impedance measured by the V/I slope is greater than 23.7kΩ and less than 26.25kΩ, the PD device is considered to be present. If the impedance is less than 15kΩ or greater than 33kΩ, the PD is considered not to exist and no further voltage is applied.

Classification mode: In order to classify the PD according to the target power level, the PSE also delivers a voltage between 14.5 and 20.5Vdc to the PD. The PD's classification is determined by the current drawn by the PD at this voltage, as summarized in the table below.

Additional Input Characteristics

In addition to the signature and classification circuitry, the PD must also include circuitry to limit the inrush current from the PSE to 400mA when the input voltage is present, and to prevent any quiescent current or impedance introduced by the DC/DC converter from being ignored during the signature and classification process.

Specific Signature/Classification Circuit

Referring to the schematic shown in Figure 1, the input signature and classification circuitry is designed around several discrete and low-cost ON Semiconductor devices, including the TL431 programmable reference circuit, 2N7002 signal level MOSFET, 2N5550 NPN transistor, NTD12N10 MOSFET, and several Zener diodes and resistors and capacitors. To implement signature detection, a 24.9k resistor (R1) is placed directly at the input. It is important to note that during the signature detection phase, the input voltage is below 10V and the constant current source formed by U1, Q2, and R4 is off because the 9.1V breakdown voltage must be exceeded to complete the biasing of this circuit. Also note that the input switch MOSFET Q3, which is connected in series with the return leg of the DC/DC converter, is also off until the input voltage exceeds about 27V. This voltage is equal to the sum of the breakdown voltage of D2 and the gate threshold voltage of Q3.


Figure 1: Schematic diagram of PoE powered device (PD).

As the voltage rises to the classification level, D1 will turn on when the voltage exceeds about 9.8V, and the current source composed of U1, Q2 and resistor R4 is turned on, and the current is accurately controlled by the U1 reference voltage (2.5V) and the classification resistor R4.

Once the classification is completed and confirmed, the input voltage can jump to the nominal value of 48V. Once this voltage exceeds the sum of the gate threshold of Q3 and the breakdown voltage of D2, Q3 begins to turn on. However, Q3 does not turn on suddenly, due to the RC time constant composed of R6 and C2, it will immediately enter the linear region. Immediate operation in the linear region can limit the inrush current because Q3 is equivalent to a resistor during this time. D3 clamps the voltage on the gate of Q3 to 15V, and R5 provides a discharge path for C2 when the input from the PSE is turned off. MOSFET Q1 is turned on at the same voltage as Q3, which turns off the U1/Q2 current source, thereby reducing the additional leakage current from the input.

Working Principle of DC/DC Converter

The DC/DC converter is designed using a monolithic NCP1031 switching regulator chip (U2) from ON Semiconductor. At a maximum output power of 5.0W, the converter is configured in a discontinuous mode (DCM) flyback topology using a common TL431 and an optocoupler voltage feedback mechanism. Modifying the transformer design and the control loop compensation network to operate in a continuous conduction flyback mode can increase the output power to 6.5W (1.3A). A differential mode π filter consisting of C3, L1 and C4 is used at the input. The control chip starts

when the undervoltage terminal of pin 6 exceeds 2.5V. The resistor divider network consisting of R7, R8 and R9 sets the chip's undervoltage and overvoltage levels to 35V and 80V respectively. Pin 8 provides internal startup bias and drives a constant current source to charge Vcc capacitor C7. Once U2 is turned on, the auxiliary winding of transformer T1 (pins 2, 3) provides operating bias through diode D1 and resistor R11.

The voltage spike caused by leakage inductance T1 is clamped by the network consisting of C5, D6 and R10. The actual power rating on R10 is a function of the primary to secondary leakage inductance of T1, and the lower the better. Capacitor C6 sets the switching frequency of the converter to approximately 220kHz.

Since secondary isolation is required, TL431 (U4) is used as an error amplifier to form a voltage sensing and feedback circuit together with the optocoupler (U3). The internal error amplifier in U2 has been disabled by grounding the voltage sensing pin 3, and the amplifier output compensation node at pin 4 is used to control the pulse width through the optocoupler's light resistance. The sensed output voltage is divided down by R16 and R17 to the 2.5V reference level of the TL431, and C9 and R15 set the closed-loop bandwidth and phase margin for DCM operation. If configured for CCM flyback operation, additional components (C14, C15, and R12) are required to stabilize the feedback loop. C8 on the primary side provides noise decoupling and additional high-frequency roll-off to U2. This implementation provides output regulation better than 0.5% for both line and load variations and closed-loop phase margin better than 50°C.

Output rectifier D5 is a 3A Schottky device for improved efficiency, and its output voltage is filtered by a π network consisting of C11, L2, and C12. Typical peak-to-peak noise and ripple of the filtered output are less than 100mV under all normal load and line conditions. C13 provides additional high-frequency noise attenuation. Typical input-to-output efficiency is about 75% under full load conditions (Figure 2). Higher efficiency can be achieved by replacing D5 with a MOSFET-based synchronous rectification circuit (ON Semiconductor's application note AND8127 details how to implement a simple synchronous rectification circuit for a flyback topology).



Figure 2: Efficiency vs. output power.

Overcurrent protection is provided by an internal peak current limit circuit in the NCP1031. When configured in CCM flyback mode at 25°C, the circuit can provide 1.3A of continuous output current before overcurrent and/or overtemperature limiting functions are activated, with inrush currents as high as 1.5A. When configured in discontinuous mode, the current is limited to about 1.0A, with peak currents up to 1.2A.

Electromagnetic Design

The flyback transformer design for discontinuous mode is shown in Figure 3, and the transformer design for continuous mode is shown in Figure 4. In flyback transformer design, it is important to keep the windings in a single layer and evenly spaced over the window length of the core structure to minimize leakage inductance. This is easily achieved in this case using a small EF16 ferrite core from Ferroxcube.


Figure 3a: Discontinuous mode flyback transformer description.



Figure 3: Discontinuous mode flyback transformer design.



Figure 4a: Continuous mode transformer description.


Figure 4: Continuous mode transformer design.

Discontinuous vs. continuous mode operation

Table 1: Ethernet power class classification.


In discontinuous mode flyback operation, the inductor current drops to zero before the MOSFET switch turns on again. This operation allows the output to have a first-order filter network, so the feedback loop stabilization circuit is simple, wide bandwidth and good output transient response can be achieved. Unfortunately, this mode of operation produces a high peak switch current and limits the output power of the circuit due to the internal current limit set point and thermal protection circuit in the NCP1031. In continuous current mode operation, the MOSFET can return to the on state before the inductor current reaches zero, so the peak switch current is lower and higher output power can be achieved without overcurrent protection intervention. However, this mode of operation also has a price, that is, the control loop bandwidth must be made lower, so the transient response to load and line changes is poor. The CCM operation mode introduces a right half plane zero in the power topology response characteristics, which requires compensation with additional feedback components as shown in Figure 2 to obtain appropriate feedback stability. Since the output rectifier must be forced to turn off the rectification function at this time, CCM will also generate more electromagnetic interference.