Detecting LDMOS drain voltage to determine whether there is overcurrent

1 Introduction

Since the power adapter chip is embedded or needs to be connected externally to the power LDMOS tube, the LDMOS tube in the application needs to be directly connected to the high voltage and pass a large current (the current LDMOS tube can withstand high voltages of hundreds or even nearly 1,000 volts). Therefore, how to ensure the safe operation of the chip and LDMOS tube is one of the key points of chip design.

Using the negative temperature characteristic of the on-chip diode forward voltage drop to monitor the thermal state of the chip and then control the switching of the power LDMOS tube is a feasible safety design method. However, due to the thermal inertia of the silicon chip, it is not possible to achieve instant control. This method is more suitable as the second line of defense for safety design.

From the perspective of chip design, to ensure the safety of the adapter chip, a better method should be to directly monitor the large current flowing through the LDMOS tube or the drain voltage of the LDMOS tube to monitor the working status of the chip in real time. Generally, two solutions are adopted: (a) a small resistor is connected in series with the source end of the power MOS tube to the ground to detect the source current, as shown in Figure 1 (a); (b) the drain voltage of the LDMOS is monitored through a detection circuit, as shown in Figure 1 (b). The former solution has at least the following disadvantages: (1) due to the discreteness of the process, it is difficult to achieve an accurate resistance value (the error is about 20%); (2) after the source is connected in series with the resistor, the tube voltage drop of the LDMOS tube with a large on-resistance is further increased, and the power handling capacity is weakened; (3) a large current flows through the resistor, consuming unnecessary energy and reducing the conversion efficiency of the switching power supply.

Figure 1 (a) Series resistor current detection Figure 1 (b) Direct detection of drain voltage

The latter solution uses the characteristics of integrated circuits (the resistance ratio accuracy of the voltage sampling circuit can easily reach 1%), so the circuit processing is not too complicated. The important thing is that the LDMOS tube has no source series resistance, which can reduce energy loss, does not affect the power handling capacity of the LDMOS tube, and improves the power conversion efficiency.

The design idea of ​​directly detecting the drain voltage to determine whether the LDMOS is overcurrent is to detect the LDMOS drain voltage through the sampling circuit when the LDMOS tube is turned on. After comparison, the overcurrent comparator outputs a low-level overcurrent signal to turn off the LDMOS tube; during the LDMOS tube cut-off period, the sampling circuit does not work, and at the same time, the comparator window level is appropriately raised to improve reliability.

2 Circuit Design

2.1 Overcurrent Comparison Module

The overcurrent comparison module is mainly composed of leading edge blanking Leadedge, sampling circuit Sample, comparison voltage generator ToCompare and overcurrent comparator Comparator, as shown in Figure 3.

Due to the influence of on-chip parasitic or external capacitors and inductors, a spike voltage will appear at the drain output of the LDMOS tube at the moment the LDMOS tube is turned on, which may cause a misjudgment of overcurrent. A leading edge blanking circuit must be added, that is, a time delay is generated for the gate control voltage of the LDMOS tube, so that the overcurrent comparator is locked at the moment the LDMOS tube is turned on. After the spike passes, the LDMOS tube drain signal is sampled and measured and the overcurrent is judged, thereby eliminating the influence of the drain voltage spike. As shown in Figure 3, we add an NMOS tube biased at a fixed voltage V (BIASN), which is equivalent to a fixed current source to limit the time for the capacitor to discharge.

Figure 3 Overcurrent comparison module circuit diagram

Reasonable design of relevant device parameters can control the size of the delay time.

The sampling circuit uses a switch control circuit to implement periodic voltage sampling of the LDMOS drain terminal, wherein the voltage divider circuit can adopt a large resistance ratio circuit structure. According to the characteristics of the integrated circuit, the error of the resistance ratio can be easily controlled within the range of 1%.

When the gate voltage V (GATE) of LDMOS is high, that is, the LDMOS tube is turned on, the sampling switch tube M10 (with higher withstand voltage and lower on-resistance characteristics) in Figure 3 is also turned on, and the saturated drain voltage of the LDMOS tube begins to be collected at the same time; when the gate voltage V (GATE) of the LDMOS tube is low, that is, the LDMOS tube is turned off (non-overcurrent phenomenon), the sampling circuit does not work.

The circuit working principle of the comparison voltage generator is as follows: Since the overcurrent state only occurs when the gate of the power LDMOS tube is in a high level state. Therefore, when V(GATEDelayed) is at a low level, I1, I2 and I3 will charge the capacitor Ccompare at the same time, so that the comparison voltage V(Compare) value increases. Considering that the maximum value of the sampling voltage is 2.5V, in order to avoid misoperation, the comparison voltage value can be set to 2.7V, so that the threshold level of the subsequent comparison circuit is increased and the anti-interference ability is improved; at the same time, the sampling capacitor Csample will be quickly discharged through the resistor R2, so that the sampling voltage V(Sample) quickly becomes zero, that is, the corresponding output is in a non-overcurrent state.

When the gate voltage V(GATEDelayed) is at a high level, the output comparison voltage becomes V(Compare)=I1×R3=1.0 V.

Overcurrent comparator The overcurrent comparator uses the common NPN differential pair input mode and constant current source bias. Slightly different from the traditional constant current source bias is the addition of a MOS switch in the bias circuit. When V(GATE) is high (at this time, LDMOS and the MOS switch are turned on at the same time), the constant current source on the left side of the circuit diagram works, making the total bias current larger, the drive current of the output buffer stage increases, and the comparison circuit speed increases; when V(GATE) is low, the constant current source on the left does not work, the total bias current becomes smaller (at this time, LDMOS is not turned on, and the overcurrent comparator is in an idle state), which is an energy-saving mode.

2.2 Control Logic

The control logic module is shown in Figure 4. This module directly controls the switch of LDMOS. The rising edge of the PULSE signal corresponds to the start of the CLOCK clock. The relationship between the PULSE signal and the clock CLOCK is shown in Figure 9. When overcurrent occurs, the OVERCURRENT signal is low, the trigger R end is high, Q is low, and the GateSwitch signal is low, turning off the LDMOS, thereby realizing the overcurrent protection function.

Figure 4 Control logic circuit diagram

3 Simulation Results

We used the BCD high voltage process to perform circuit simulation verification in the cadence environment. The results are as follows:

Simulation conditions of the leading edge blanking circuit: the power supply voltage is 5.8 V, the 2 pF capacitor has a discharge current of 10 μA, and the delay time is Tdelay=C*0.

5VDD/I =2p*2.9/10μ= 0.58μs. The simulation results are shown in Figure 5.

Figure 5 Leading edge blanking circuit simulation

Simulation of sampling circuit

Assuming that the voltage at the detection end generally varies between 10 and 50 V, we set V(Detect)=SIN(30,20,50 k); the period is 20μS; and the comparison voltage is 1 V during the sampling period; according to the conduction characteristics of the LDMOS tube, if the output drain voltage is higher than a certain value (20 volts in this case), it is considered overcurrent, then the voltage divider ratio is designed to be K = R4/ (R3+R4)=5 k/(5 k+95 k)=1/20, so the sampling voltage value is V(Sample)=V(Detect)*k =SIN(1.5,1,50 k), that is, the maximum value is 2.5 and the minimum value is 0.5. Similarly, we add a capacitor to the output of the sampling circuit to eliminate the influence of voltage spikes. The simulation results of the sampling circuit are shown in Figure 6.

Figure 6 Sampling circuit simulation

Comparative Voltage Generator Simulation

A capacitor Ccompare should be added to the output of the comparison voltage generator to eliminate the peak voltage generated at the Ccompare terminal when the switch is turned on. The simulation results are shown in Figure 7, where the dashed/solid lines are the simulation results with and without the capacitor. Obviously, the presence of capacitor Ccompare greatly improves the output waveform. The selection of the size of capacitor Ccompare should weigh the relationship between the peak elimination effect, charging speed and chip area consumption.

Figure 7 Comparison before and after adding capacitor Ccompare

In this example, Ccompare is set to 4 pF. Simulation of the overcurrent protection circuit module

The circuit of Figure 3 is simulated, with the power supply voltage VCC being 5.8 V, the LDMOS drain detection voltage being between 10 and 50 V, the gate voltage pulse frequency being 132 kHz, and the duty cycle being a square wave of 60%. The SPICE simulation conditions are set as VCC=5.8 V, V (Detect)= SIN(30,20,50k), and V (Gate)=PULSE(0,5.8,0.5u,0.5u,0.5u,3u,7u). The simulation results are shown in Figure 8. In the two sampling intervals of 1.26 uS~4.17 uS and 8.25 uS~11.2 uS, the sampling voltage V(Sample) is larger than the comparison voltage V(Compare), and the output is low level (overcurrent protection, low level is valid); in the sampling interval of 15.2 uS~18.2 uS, the sampling voltage V (Sample) is smaller than the comparison voltage V(Compare), and the output is high level, corresponding to no overcurrent; in other time periods, the gate voltage is at a low level, corresponding to the LDMOS in the off state, and overcurrent is impossible, so the overcurrent output signal OverCurrent is high level. The simulation results show that the circuit can indeed achieve the function of overcurrent protection.

Figure 8 Overcurrent protection circuit simulation results

Simulation of control logic circuits

In the control logic shown in Figure 4, the clock CLOCK is set to PULSE (0,5.8,0,0,0,4u,7u), and the overcurrent signal OVERCURRENT jumps from high level to low level at 15us for simulation. The PULSE signal records the start of the CLOCK signal and periodically detects the overcurrent signal. When the overcurrent signal OVERCURRENT is valid at a low level, R is high, and the RS trigger output Q is reset to a low level. At this time, FC is high, and the gate control signal GateSwitch output is low, turning off the LDMOS. The simulation results are shown in Figure 9(b).

Figure 9 Simulation of control logic circuit

Overall simulation of closed-loop control circuit

As shown in Figure 10, the circuit in Figure 3 and the external LDMOS form a closed-loop control system. The simulation results are shown in Figure 11: When there is no overcurrent, the duty cycle of the gate voltage is the largest; when overcurrent occurs, the overcurrent signal OverCurrent forces the gate voltage to a low level and turns off the LDMOS, thereby achieving an overcurrent protection effect.

Figure 10 Closed-loop overall simulation schematic

Figure 11 Closed-loop overall simulation waveform

3 Conclusion

This article describes several overcurrent detection methods and analyzes the advantages and disadvantages of each method. A closed-loop control overcurrent protection circuit is designed. It uses the method of directly detecting the drain voltage of the LDMOS tube to overcome the disadvantages of energy consumption and chip heating when using resistor detection, while improving the energy conversion efficiency of the switching power supply DC/DC. In addition, the ratio sampling circuit design is adopted to overcome the influence of process deviation and improve the sampling accuracy.

Based on the 3μm high-voltage BCD process, we used the circuit simulator Spectre in the Cadence design environment to simulate the control circuit in both sub-modules and overall modules. The results show that the circuit can well implement the real-time overcurrent protection function.