Design of Mixed Voltage System Based on Low Voltage CPLD EPM7512A

introduction

With the rapid development of microelectronics technology, low-voltage chips with smaller size, lower power consumption and better performance are emerging. I/O level logic is developing towards 3.3V, 2.5V, 1.8V, and even lower. However, for decades, since 5V power supply devices have always occupied a relatively important market, they often coexist on a circuit board in system design. Therefore, in the process of designing them, it is inevitable to encounter interface problems with different voltage levels.

1 EPM7512A Overview

EMP7512A is a CPLD (Complex Programmable Logic Device) of the MAX7000A series launched by Altera. It uses CMOS EEPROM technology, with a transmission delay of only 3.5ns, and can realize a counter with a frequency of up to 200MHz. It has rich internal resources - 512 triggers and 10,000 user-programmable gates. In order to be more suitable for mixed voltage systems, it provides 2.5V and 3.3V voltage cores. Through configuration, the input pins can work compatible with 2.5V/3.3V/5V/logic levels, and the output can be configured as 2.5V/3.3V logic level output. EPM7512A also provides a JTAG interface for ISP programming, which greatly facilitates users.

2 Power Supply Design

In this system, the power supply provided by the outside world is ±12V and +5V, and the working voltage of EPM7512A needs to be 3.3V, so the power supply problem must be solved first. The following are several solutions.

(1) Use low voltage dropout linear regulator chip
Linear regulator chip is the simplest power conversion chip, which basically does not require peripheral components. It is easy to use, low cost, small ripple, and no electromagnetic interference. However, traditional linear regulators, such as the 78xx series, require the input voltage to be 2V to 3V higher than the output voltage, otherwise it will not work properly, so the 78xx series can no longer meet the requirements of 3.3V power supply design. In response to the demand for low voltage power supply, many power chip companies have launched low voltage dropout linear regulator LDO (Low Dropout Regulator). The voltage drop of this power chip is only 1.3V to 0.2V, which can achieve 5V to 3.3V/2.5V, 3.3V to 2.5V/1.8V and other requirements.

(2) Designing a switching power supply
A switching power supply is also a method of achieving power conversion, and it is very efficient, but the design is much more complicated than using a linear regulator. However, for designs with high current and high power, a switching power supply is recommended. The synchronous rectification technology in the current switching power supply can effectively solve the problem of low voltage and high current.

(3) Resistor voltage division
This method is simple and low-cost, but the voltage division output is affected by the load size and is not recommended for use in low-voltage systems. After comprehensive comparison of the above solutions, TI's LDO chip TPS7333QD was selected, with a load capacity of 500mA, which meets the system power consumption requirements.

3 Logical Interface Design

(1) Conversion standards for various levels
The power supply voltage of EMP7512A is 3.3V. When VCCINT is connected to 3.3V, the logic level range of the input port is -2V to 5.75V. The logic level range of the output port is 0V to VCCIO. VCCIO can be connected to 2.5V or 3.3V. When designing a CPLD system, in addition to the CPLD itself, there are many peripheral modules and chips, such as Flash, D/A, A/D, etc. These can be divided into two categories - the 5V level that drives the CPLD and the 5V level chip driven by the CPLD. Therefore, there is a problem of how to reliably interface the low-voltage CPLD with these chips or modules. Table 1 lists the conversion standards for 5V CMOS, 5V TTL and 3.3V levels. Among them, VOH represents the lowest voltage of the output high level, VIH represents the lowest voltage of the input high level, VIL represents the highest voltage of the input low level, and VOL represents the highest voltage of the output low level. As can be seen from Table 1, the conversion standards for 5V TTL and 3.3V are the same, while the conversion standards for 5V CMOS are different. Therefore, when interfacing a 3.3V system with a 5V system, the differences between the two must be taken into account.

(2) Problems with interfaces when logic levels are different
In mixed voltage systems, there are several problems with interfaces between logic devices with different power supply voltages.

① The maximum voltage limit allowed on the input and output pins. Devices usually have limits on the voltage applied to the input or output pins. These pins are connected to Vcc by diodes or discrete components. If the voltage connected is too high, the current will flow to the power supply through the diode or discrete component. For example, if a 5V signal is added to the input of a 3.3V device, the 5V power supply will charge the 3.3V power supply. The continuous current will damage the diode and other circuit components.
② The problem of the mutual current between the two power supplies. When in the waiting or power-down mode, the 3.3V power supply drops to 0V, and a large current will flow to the ground. This causes the high voltage on the bus to be pulled down to the ground, causing data loss and component damage. It must be noted that no matter in the 3.3V working state or in the 0V waiting state, current is not allowed to flow to Vcc.
③ The problem of interface input conversion threshold. There are many different situations when using 5V devices to drive 3.3V devices. Similarly, there are different situations for the conversion level between TTL and CMOS. The driver must meet the input transition levels of the receiver with enough margin to avoid damaging circuit components.

(3) Four situations of EPM7512A and 5V level interface
In this system, there are four different situations to consider. (Configuration pins VCCINT and VCCIO must be connected to 3.3V to configure EPM7512A as a 3.3V TTL device.)

① 5V TTL device drives EPM7512A (direct connection). Since the level conversion standards of 5V TTL and 3.3V are the same, the typical value of 5V TTL device output is 3.6V. Therefore, if the 3.3V device can withstand the voltage of 5V, it can be directly connected from the level point of view. EPM7512A can withstand 5V TTL level drive.
② EPM7512A drives 5V TTL device (direct connection). Since the VOH and VOL levels of 3.3V devices are 2.4V and 0.4V respectively, the VIH and VIL levels of 5V TTL devices are 2V and 0.8V respectively; and EPM512A can actually output a voltage with a swing of 3V. Obviously, 5V TTL devices can correctly identify the input level of EMP7512A.
③ 5V CMOS device drives EPM7512A (direct connection). Analyzing the conversion levels of VOH and VOL of 5V CMOS and VIH and VIL of 3.3V, we can see that although there are certain differences between the two, 3.3V devices that can withstand 5V voltage can correctly identify the level value sent by 5V devices. Therefore, the input end of 3.3V devices that can withstand 5V voltage can directly interface with the output end of 5V devices. EPM7512A has a 5V tolerance, so it can directly interface with the output end of 5V devices.
④ EPM7512A drives 5V CMOS (cannot be directly connected). The level conversion standards of 3.3V and 5V CMOS are different. As can be seen from Table 1, the minimum voltage value of the high voltage output of 3.3V is VOH = 2.4V (the maximum output voltage can reach 3.3V), while the minimum high level voltage VIH = 3.5V required by 5V CMOS devices, so the output of EMP7512A cannot be directly connected to the input of 5V CMOS devices. Some processing must be done for this. The most common method is to use a level interface conversion chip to achieve mutual conversion between 3.3V and 5V levels. A bidirectional driver powered by dual voltage (3.3V on one side and 5V on the other side) can be used to achieve level conversion. Chips such as TI's SN74ALVC164245 and SN74ALVC4245 can better solve the problem of 3.3V and 5V level conversion. For 5V TTL or 5V CMOS devices, if you drive a 3.3V (but no 5V tolerance) device, you cannot connect directly, but you can also use SN74ALVC16245 to achieve 5V to 3.3V conversion. For the case of EPM7512A driving 5V CMOS, there is another better method, which is to make the output port OC (open collector) output, and connect a resistor outside to pull it up to 5V, so that you can drive 5V CMOS devices, but the logic is reversed.

4 Conclusion

Hybrid logic systems will exist for a relatively long time. Their design is relatively complex, and the logic interface problems must be carefully analyzed, otherwise the chip may be burned or the logic may be distorted. The author has summarized these methods in the process of applying EEM7512A, which have universal significance for the design of hybrid logic systems.