Wireless network system design based on STM32L152 and S14432

In modern life and production, wireless communication technology is increasingly used. Various instruments and meters in complex environments such as residential areas, hospitals, and factories can collect and monitor data through wireless networks. The control and collection of industrial field automation data requires a wireless communication network with a transmission distance of about 1 km, low power consumption, simplicity, reliability, and low price. The communication distance of the wireless transceiver chip S14432 can reach 1 to 2 km. This paper designs a wireless network system based on STM32L152 and S14432. The system uses the low-power, high-performance Cortex-M3 core 32-bit microcontroller STM32L152 and the highly integrated, low-power wireless transceiver chip S14432, which is suitable for short-distance field data collection and monitoring. The system adopts network management and uses master node backup technology and LEPS routing protocol to ensure the reliability and scalability of the system.

1 Main control chip

STM32L152 is an ultra-low power, high data security, and high-performance ARM Cortex-M3 microcontroller series chip provided by STMicroelectronics. The STM32L15XXX series chips use STMicroelectronics' EnergyLite ultra-low power platform, and can complete tasks at the lowest power consumption at any set time through 6 ultra-low power modes. The controller has a low-power operation mode current of 10.4μA, an operating voltage of 1.8 to 3.6 V, a minimum operating voltage of 1.8 V for on-chip analog functions, and a minimum operating voltage of 1.65 V for digital functions. The operating temperature range is -40 to +85°C, and the processing performance at 32 MHz frequency reaches 33 DMOPS (maximum), with flexible undervoltage reset, on-chip flash memory supporting error correction code (ECC), memory protection unit (MPU) and JTAG fuse. The ARM Cortex-M3 processor it uses can provide excellent computing performance and excellent system response to events, while meeting the challenges of dynamic and static power constraints.

The system uses the STM32L152 chip, 48-pin LQFP package. The chip has 128 KB Flash, 16 KB RAM, 4 096 bytes of E2PROM and 8 16-bit timers; it integrates a variety of peripheral modules, including 12-bit ADC, 12-bit DAC, comparator, SPI, I2C, LCD, USB, etc.

2 Architecture of wireless network system

The architecture of the wireless network system is shown in Figure 1. The system is a tree topology network consisting of a master node and multiple slave nodes. The master node builds and manages the entire wireless network, transmitting control instructions to slave nodes and receiving data information from slave nodes. The slave node receives control instructions from the master node and transmits data information to the master node.

3 System Hardware Design

The hardware structure of the wireless network system is shown in Figure 2. The master node, backup master node and slave node all use the same hardware circuit. The STM32L152 microcontroller controls SI4432 to realize the transmission and reception of wireless data. The RF transceiver chip used is the SI4432 chip launched by Silicon Labs. This chip is a highly integrated, low-power EZRadioPRO series wireless transceiver chip. Its operating frequency band is 240~960 MHz, and the receiving sensitivity reaches -117 dB, which can provide excellent link quality, while expanding the range and reducing power consumption to a minimum, the maximum output power can reach +20 dB, and the transmission distance can reach 2km.

The main control chip sTM32L152 uses a high-speed external clock signal (HSE) and selects three boot modes through BOOT0 and BOOT1. The chip can use STM studio, Keil MDK-ARM and other compilation tools, and has a 20-pin JTAG interface that can use ST-LINK and ULINK2 emulators. The main control circuit communicates with the control system through an RS232 interface. The hardware circuit of the main control chip is shown in Figure 3.

STM32L152 is connected to SI4432 through a standard SPI interface. The main control chip initializes and configures the internal registers of the RF chip through the SPI interface, and sends control instructions and read and write data information. SI4432's SDN, NIRQ, NSEL, GPIO0, GPIO1, GPIO2, etc. are connected to the main control chip. The SDN pin is the working mode bit, the NIRQ pin is the interrupt status output, the NSEL pin is the chip select signal, and GPIO1 and GPIO2 are the antenna selection bits. The RF circuit operates in the central frequency band of 470 MHz. 470~510 MHz is a wireless metering frequency band that is exempt from application by the national radio management department. The hardware circuit of the RF chip is shown in Figure 4.

The entire wireless network uses only one master node, and hardware redundancy technology is used in the design. A backup master node is set at the master node. The backup master node is a replica of the master node, has the same control and management as the master node, and has the same level of master node address. When the control system detects that the master node fails, the redundant master node can be activated to replace the master node to ensure the normal operation of the entire wireless network system.

4 System Software Design

The software design of the system is divided into two parts: the master node and the slave node. The software design adopts the design idea of ​​functional modularization. The system can be divided into initialization module, application module and network management module. The initialization module includes the microcontroller initialization module, the RF chip initialization module and the application initialization module; the application module includes the wireless transmission module, the wireless receiving module, the data processing module and the working mode module; the network management module is to form a wireless network through the routing protocol.

4.1 System Initialization

After the system is powered on, the MCU initializes the hardware and functional modules according to the difference between the master node and the slave node, sets the function of each pin, the working mode and resource allocation of the MCU, and the initialization of each application functional module. Then, the wireless RF chip is initialized through the SPI interface. The working mode, frequency, transmission speed, transmission method, etc. of the RF chip are set according to the master and slave nodes.

4.2 Data Processing

The system uses a frame format similar to the ZMAC protocol to package data for communication. The format of the data packet is as follows:

The 8n-bit preamble is added to the front of the data packet to enable the receiving end to perform frame synchronization. The preamble is followed by the frame synchronization word. When the receiving end receives the frame synchronization word, it starts to receive data. The packet length and check code are used by the receiving end to check whether the data is received incorrectly. The data processing module is responsible for information processing of the data packet before sending and after receiving. The data packet is divided into network maintenance class and information class, which are distinguished by the packet type bit, and the information of the data bit in the data packet is not accessible. When the network system is in the formation and maintenance period, the data packet belongs to the network maintenance class, and the information of the data bit is the routing information of the node. The routing information of the node includes the number of hops to the aggregation node, the link quality assessment information to the adjacent node, the node number, etc. When the network system is in working state, the information of the data bit is control instruction or data code. Before the node sends the data information, the data processing module is responsible for classifying the data information to be sent, and then adding various different bit information to it to form a mature data packet to be sent. After the node receives the data information, the module is responsible for verifying the data packet, classifying the data packet, and then separating and sorting the various information bits. Among them, when sending and receiving, the configuration bit can be directly separated by configuring the SI4432 register. The configuration bit structure is as follows:

4.3 Data transmission and reception

The data transmission module is responsible for sending data packets. When receiving the transmission instruction, first clear the transmission FIFO of the RF chip through SPI, and then write the data to be sent into the transmission FIFO. Turn on the RF chip transmission completion interrupt and disable all other interrupts. The microcontroller enables the transmission function of the RF chip, and the data starts to be transmitted wirelessly. Pull the IRQ pin high and wait for the wireless transmission completion interrupt. If the data is successfully transmitted, NIRQ becomes low.

The data receiving module is responsible for receiving data packets. When receiving the receiving instruction from the microcontroller, first clear the receiving FIFO of the RF chip through SPI. Turn on the preamble code reception, frame synchronization interrupt and receive packet data valid interrupt, and turn off other interrupts. Get ready to start receiving. If the pin NIRQ becomes low and the receive packet data valid interrupt bit is read, read the data in the receive FIFO through SPI and turn off the receive function. The sending and receiving program flow is shown in Figure 5.

4.4 System Management Mechanism

The wireless network consists of master nodes and slave nodes. It is a tree topology with the master node as the root center. The management of the entire network is completed through the network management module in each node. The wireless network adopts the LEPS (Link Estimation and Parent Selection) protocol. The LEPS protocol is a multi-hop routing protocol of the TinyOS system. It exchanges neighbor information between nodes.

The mechanism considers the link quality and establishes the shortest communication path to the central node.

The slave nodes are divided into parent nodes of different levels. They only send information to their own parent nodes, and then upload to the master node through the parent nodes step by step. The slave node routing table has the number address of its own child node. The parent node is the center of the network and is the highest level parent node. Its routing table has the number and address of the entire network node. The data of the master node is transmitted to each slave node step by step by its child nodes.

Wireless networks are divided into three stages: topology establishment, route maintenance, and data communication. In the topology establishment stage, all nodes periodically broadcast their routing information. Nodes establish the shortest route and the routing table based on the number of hops and link quality information. The network will be regularly maintained. During the maintenance process, the node will evaluate the parent node again and refresh the routing table. In the data communication stage, the routing protocol provides a path for data transmission. After the network is completed, if nodes are added to the network, it is only necessary to maintain and update the network and update the routing table.

4.5 Parent Node Selection

All slave node data is transmitted to the master node through the parent node. Parent node performance is the core part of the routing protocol. The selection of parent node depends on the link quality and the number of hops.

Link quality is the quality of bidirectional link communication between two nodes. Take two adjacent nodes A and B as an example. In the network broadcast information, node A sends multiple sets of data to node B. The reception success rate of node B is:

The protocol further uses the weighted unique average method to calculate the final link quality estimate, thereby reducing the jitter of the link quality assessment. Let the new link estimate be NEWEST, and the proportion be μ=25%, then the original combat proportion is (1-μ), and the final link quality estimate is:

The hop count HOPNU is the total number of forwarding times from the node to the master node. In the network, due to the link quality, the parent node of the node may be lost. When selecting the parent node, in order to ensure the quality of the parent node, the link quality of SEDEST>0.1, RCVEST>0.1 and EST>0.16 is usually selected, so that the link quality is not too low and unstable. Then, among the adjacent nodes, the minimum hop count is first determined, and then the link communication quality is determined to select the parent node.

Conclusion

The STM32L152 main control chip and SI4432 wireless transceiver chip used in this system are both low-power and highly integrated chips, which reduce the power consumption of the system. Among them, STM32L152 is a Cortex-M3 microcontroller, which improves the performance of the system; the master node has hardware backup to improve the reliability of the system; LPES routing protocol technology improves the communication efficiency of the system and makes the system easy to expand. This system is suitable for some short-distance communication applications such as industrial field data collection, community data collection, hospital ward monitoring, and agricultural field data collection. Functional modularization and network scalability make the system easy to update functions and expand nodes.