EPS energy-saving "reform" plan

In recent years, power supply products have made breakthrough progress, but at the same time, the problem of energy waste has become a growing concern at home and abroad, which is reflected in the following aspects:

a Energy resources using fossil fuels are limited, the cost of obtaining energy is increasing, the consumption of fossil fuels also brings other negative effects (i.e. environmental pollution), and alternative energy resources are not yet mature.

b All home appliances and electronic devices consume electricity.

c The growing number of personal electronic products also consumes energy through the use of adapters and chargers - external power supplies (EPS).

1. Energy-saving concept to promote or redesign

High efficiency of the power supply at light load is the key factor. The efficiency of the working mode is the average of the efficiency when the power supply is working at 25%, 50%, 75% and 100% load: continuous high efficiency over the entire load range is more important than high efficiency at heavy load; the ideal control scheme is to reduce the frequency accordingly as the load decreases.

In order to provide higher energy efficiency for power supply systems, many standards have been promulgated internationally, such as the International Energy Agency's "1W Plan", the US new Energy Star, and the US 80 PLUS.

New external power supply (EPS) energy efficiency standard: Applicable to all single-channel output external power supplies (EPS) with power ranging from less than 1W to 250W; Equivalent to EnergyStar (EPA) standard (CEC, CECP, AGO, EU); Applicable to both AC-DC and AC-AC adapters and chargers; Other states in the United States will also use this standard/regulation in progress; China's CECP standard will take effect from January 1, 2005; It will take effect in Australia from April 1, 2006; The EU will also adopt the corresponding provisions for the working mode in the standard from January 1, 2007.

With the introduction of these new standards, new challenges have been posed to power supply design. To this end, new measures are needed to face the new challenges. The first is to use energy-saving concepts to promote or redesign. That is, energy saving has become an important design requirement; 60% of existing solutions today cannot meet the requirements of the new standards; energy-saving standards for external power supplies (EPS) have been promulgated; many companies have launched new product series that can make your design meet all current and proposed standards. In addition, new technologies must be used to meet design challenges. For example, in order to reduce energy consumption in standby mode, ON Semiconductor focuses on other technologies, such as skip cycle standby mode, PWM controller master PFC (turn off PFC when light load to reduce standby energy consumption). In addition, integrating many new technologies and functions into the chip, such as DDS (dynamic self-powered), frequency jitter, Soxy-less (no coil demagnetization detection), etc., can simplify the design of peripheral circuits and reduce power loss accordingly. This is worth studying only two aspects: selecting energy-saving chips and using intelligent power management technology to save energy.

2. Selection of energy-saving chips

2.1 LinkSwitch-LP device features and working mode

2.1.1 LinkSwitch-LP Series Product Features

Easy to design, low-component solution; primary circuit controller limits output current when load exceeds peak power point - no current sense resistor required; complete fault protection - overheating, short circuit and open loop; can operate within universal input voltage range (85-265VAC); Figure 1 shows the simplified circuit (a) and output characteristics (b) of a typical application. The outstanding feature is energy-saving technology: no additional components are required, easily meeting all global energy-saving standards; no-load energy consumption at 265VAC input is <150mW; on/off control can achieve constant efficiency at extremely light loads - ideal for meeting mandatory CEC standards.

2.1.2 LinkSwitch-LP System Cost Advantages

From Figure 1, we can see that: frequency jitter reduces EMI, and a simple EMI filter is used; the inductor is used for both filtering and fuse function, see point A in Figure 1; the internal high-voltage constant current source eliminates the startup and bias circuits, see point B in Figure 1; the internal current detection circuit eliminates the external current detection resistor, see point C in Figure 1; strict device parameter tolerance, low current limit point, allowing the primary winding to not use a box position circuit, see point D in Figure 1; low-cost transformer feedback voltage regulation, see point E in Figure 1; the output voltage is determined by the voltage divider resistor, with an accurate FB pin voltage, see point F in Figure 1; the on/off operation does not require frequency compensation components, see point G in Figure 1. It is optimized for applications with minimum cost requirements and loose constant voltage/constant current requirements.

2.2 Typical Applications

Figure 2 shows a typical alternative solution for a 6V330mA constant voltage/constant current (CV/CC) output power supply circuit using LNK564IC. Here we analyze the characteristics of the solution.

2.2.1 Input Circuit

AC input differential mode filtering can be achieved with a very low cost input filter formed by C1 and L1. The frequency jitter characteristic of the LNK564 eliminates the input pi (C, L, C) filter components, requiring only a large capacitance capacitor. Adding a bushing also allows the input inductor L1 to be used as both a fuse and a filter component. This simple Filterfuse input stage further reduces system cost.

Another option is to use a fuse resistor RF1 to provide the fuse function.

In some applications, if lower EMI margin and/or reduced input surge withstand capability are allowed, input diode D2 can be removed from the neutral line. In such applications, D1 needs to be a diode with a withstand voltage of 800V.

2.2.2 About LNK564 on/off control

The design uses a simple bias winding (T1 pulse transformer/1.2) voltage feedback method, which is controlled by LNK564 for on/off. When the switch is off, the resistor divider formed by R1 and R2 determines the output voltage on the bias winding of pulse transformer T1. In the constant voltage operating region on the V/I curve (see Figure 1 (b)), the LNK564 device enables/disables switching cycles to maintain the voltage at the FB pin at 1.69V. Diode D3 and low-cost ceramic capacitor C3 provide rectification and filtering of the primary feedback winding (T1/3.4) voltage. When the load is increased beyond the constant power threshold, the FB pin voltage begins to decrease as the power supply output voltage decreases. The internal oscillator frequency decreases linearly in this region until it reaches 50% of the start-up frequency. When the FB pin voltage drops below the auto-restart threshold (usually 0.8V at the FB pin, which corresponds to a power supply output voltage between 1V and 1.5V), the power supply will shut down for 100ms and then restart for 100ms. It will continue in this mode until the FB pin exceeds the auto-restart threshold. This feature reduces the average output current in the event of an output short circuit. In this solution, C3 can be increased to 0.47mF or higher to further reduce no-load consumption.

The current limiting regulation technology used in LNK564 makes the current limiting point tolerance very accurate, and the newer transformer structure technology is used to achieve the design of no clamp circuit in the primary circuit. The peak drain voltage can be controlled below 550V at 265VAC input, which has a very large margin for 700V withstand voltage (BVDss) MOSFET tubes.

2.2.3 Selection of output circuit tube

The output rectification and filtering is achieved by the output rectifier tube D4 and the filter capacitor C5.

Due to the auto-restart feature, the average short-circuit output current is well below 1A, allowing the use of the low-cost D4 rectifier. The output circuit only needs to be able to handle the continuous short-circuit current when the power supply output is shorted. Diode D4 is an ultrafast recovery diode to optimize the output V/I characteristic. Optional resistor R3 acts as a dummy load to limit the output voltage when the output is no-load. Despite this dummy load, the no-load energy consumption remains within the target range of about 140mW at 265VAC. By increasing the value of R3 to 2.2kW or higher, lower no-load energy consumption requirements can be met while limiting the output voltage to less than 9V. If desired, an optional Zener clamping diode (VRl) can be installed in the blank space on the left side of the circuit board to limit the maximum output voltage of the power supply in the open loop condition.

3. Save energy with intelligent power management technology

In recent years, power management technology has made great progress, and there are more and more design options to choose from. Government environmental groups and consumers continue to put pressure on electronic product manufacturers, urging them to increase product functions while also reducing system energy consumption. At present, the development of the portable electronic product market is particularly impressive. For example, wireless communication products are constantly being innovated and their functions are becoming more and more diverse, which is the hero driving the development of the entire market. According to the current development trend, mobile phones, personal digital assistants, MP3 players, digital cameras and portable electronic game consoles are all moving towards smaller size, higher speed and more complete functions. In order to ensure that the /talk time/ (i.e. battery life) can be extended to a satisfactory level, engineers have been committed to improving the design of the power supply subsystem.

The battery life of portable electronic products depends on two key factors, one is the power conversion efficiency, and the other is the system's energy management method. The power conversion system is responsible for converting the battery supply voltage to the specified power supply mains voltage with the highest efficiency, while the energy management system provides power supply that just meets the needs of the actual application in real time to save energy.

3.1 PowerWise technology reduces energy consumption

The new generation of energy-saving technology focuses on adjusting the frequency and voltage of the processor to reduce energy consumption.

For battery-powered systems, whether the system can stay on for a long time depends on its energy consumption. Simply reducing its frequency will only reduce the average power consumption: it will not reduce the energy required for a particular computation. The system voltage must be lowered to truly save energy. Dynamic voltage scaling (DVS) and adaptive voltage scaling (AVS) are two power management technologies that can reduce the system voltage.

3.1.1 Advantages of Adaptive Voltage Scaling Technology

An embedded adaptive power controller (APC) that tracks performance changes in the system processor makes adaptive voltage adjustments. The APC accurately communicates system processor performance (frequency), temperature, and process changes to an external adaptive power management chip through a PowerWise high-speed, low-power interface. The power management unit then automatically adjusts the supply voltage of the system processor based on performance requirements. Previous voltage adjustment schemes were open-loop. The CPU controls the voltage maintained in a frequency/voltage check table and provides voltage through a dedicated interface and power management circuit. Checks whether the value in the table is a false or worst-case value. Adaptive voltage adjustment mitigates CPU interference and reduces pressure in a closed-loop manner. The adaptive power management provided by PowerWise technology combined with the accurate dynamic performance settings provided by ARM's Intelligent Energy Manager provides unprecedented ideal results.

3.1.2 Dynamic Voltage Scaling (DVS) Technology

Different combinations can be formed, and the most suitable voltage/frequency combination can be selected according to actual needs during adjustment. A variety of power management integrated circuits PMICs are available, including LP3906 and LP3907 that support DVS mode, and LP5550, P5551 and LP5552 that support both DVS and AVS modes. Dynamic voltage scaling (DVS) technology can save power and energy, and also reserve some extra space for the power supply voltage to support systems with different technologies and temperatures. Although this reserved extra space is sufficient to cope with the most circumstantial situations, it will waste more power in actual applications. As long as we turn off the power supply loop of the system, the control loop can flexibly adjust the operating voltage and reduce it to a minimum in order to save energy as much as possible. PowerWise technology uses this method to save energy.

3.2 PowerWise Features

The PowerWise interface (PW) can support intelligent energy management systems. PowerWise is an energy management technology that targets the overall needs of the system, ensuring that battery-powered electronic products can use adaptive voltage scaling (AVS) technology and control the switching of different states. PowerWise technology uses a closed-loop AVS system with a high-speed serial power management bus to ensure that the processor can use the lowest voltage at any time and at any frequency to minimize dynamic energy consumption.

PowcrWise technology can also provide bias for the processor's potential well. Since the supply voltage Vdd has been lowered to reduce dynamic losses, the threshold voltage of the transistor must also be lowered to ensure that the drive voltage can be maintained at a high level, but the disadvantage is that leakage and static power loss will increase. As long as we provide a reverse bias to the potential well, the leakage will be reduced. In addition, taking the same supply voltage (Vdd) as an example, we also provide a forward bias to the potential well to increase the drive voltage.

The standard system configuration that can support the PowcrWise closed-loop AVS function must have the following basic components: an advanced power controller built into the processor, a power management integrated circuit with a PWI slave, and a two-wire PWI serial bus that connects the two. The power management integrated circuit is responsible for providing a different voltage to the processor, and the voltage is regulated by the PWI master controller in the advanced power controller. The master controller transmits the relevant commands to the PWI slave, and then the relevant circuits make adjustments.

The advanced power controller is responsible for receiving commands from the main processor, providing an operating environment for the voltage control process that is not affected by the processor, and tracking the operating speed of the logic circuit in real time. The advanced power controller is always on alert, constantly monitoring all system parameters, such as system temperature, load, transient, process and other related changes. Whenever the advanced power controller receives a message about the upcoming frequency change, it will make a judgment in advance to determine how much power the system needs at least to operate stably at the new frequency. The entire process is monitored by a closed-loop circuit. For example, the advanced power controller first transmits the power adjustment command to the PWI slave via the PWI interface, and then the servo device adjusts the voltage to the appropriate level.

FIG3 is a schematic block diagram of a typical chip LP5552 that uses PowcrWise technology to reduce energy consumption. Its technical parameters are as follows.

The number of LP5552 outputs is 7. The output voltage and current are: 2 buck regulators with an output voltage of 0.8v to 1.235v and an output current of 800mA; 5 buck regulators with an output voltage of 0.8v to 3.3v and an output current of up to 250mA.

The input voltage range is 2.7V to 4.8V. The interface is PWl 2.0. The package is micro SMD-38.

3.3 PowerWise Technology Application

PowerWise technology is an advanced energy management solution, mainly targeting current and future digital devices that are energy-constrained, and is suitable for dual-core processors, mobile phones, portable radios, personal digital assistants, battery-powered electronic products and portable devices. It can reduce the energy consumption of digital processors by 70%, thereby extending battery life, supporting more functions and improving user experience. PowerWise uses technologies such as adaptive voltage regulation (AVS) and threshold voltage regulation to automatically minimize the working and leakage power consumption of digital logic integrated circuits while maintaining minimal system overhead.

PowerWise technology provides an optimized closed loop between the single-chip system and supporting components without CPU intervention. Embedded PowerWise technology is processor-independent because it can be synthesized.

4 Conclusion

In addition to the above two aspects of selecting energy-saving chips and using intelligent power management technology to save energy, it should be pointed out that the energy-saving technology methods for different types of products are also different. The application of power sequencing technology is also a more ideal solution. Because in many high-power systems, the cost of space and cooling systems is very high. Therefore, for any POL converter, it is extremely important to be compact, efficient and have low quiescent current to meet the new "green" standards. In addition, many microprocessors and digital signal processors (DSPs) require a core power supply and an input/output (1/()) power supply, which must be sequenced at startup. Designers must consider the relative voltage and timing of the core and I/O voltage sources during power-on and power-off operations to meet the manufacturer's performance specifications. Without proper power sequencing, latch-up or excessive current consumption may occur, which may cause damage to the microprocessor I/O port, or damage to the I/O port of supporting devices such as memory, programmable logic devices (PLDs), field programmable gate arrays (FPGAs), and data converters.