Design of LED display screen control system based on single chip microcomputer

This design uses dual RAM technology to organize the control system data for controlling the rectangular display screen , improves the memory efficiency when the information is displayed in a vertical cycle, greatly reduces the occupancy rate of the data memory, and does not require a very high refresh rate.

1. LED display Data organization

When the area to be displayed is less than or equal to the actual display area, static display can be used. However, most of the time, the area to be displayed is greater than or equal to the actual display area, as shown in Figure 1. In order to simplify the analysis of the problem, this article sets the display area height to 4 times the height of the LED display screen , and the width is equal to the width of the LED display screen. Let the height of the display screen be Lh and the width be Lw, then the display area height Dh=4Lh and the width Dw=Lw. This article uses monochrome display as the description object, and Bw=Bn=8 (Bw is the number of scan lines, Bn is the output data width), as shown in Figure 1.

For an LED display screen, once the width Lw and height Lh are determined, the arrangement of the display screen unit board is also determined. The distance between two adjacent scan lines of the unit board is Sw, and the display screen has Bw scan lines, namely Y0, Y1, ..., YBw-1. Each Sw row corresponds to one bit of display data, and each point on the display screen corresponds to a bit of a byte in the memory. The Bw scan lines point to: Y0=O, Y1=Sw, ..., BBw-1=(Bw-1)Sw. Use the static display data organization method to organize the display data for display blocks A, B, C, and D respectively. First, organize the display information of display block A (X is the column number):

①X=0, that is, the display data of each point where each row of the current scan line intersects with the Oth column is stored in the first storage unit of the memory in the order of D0, D1, ..., DBw-1.

② The X value increases by 1, and the display data of each point where each row of the current scan line intersects with the column corresponding to the X value is stored in the next storage unit of the memory, until all Dw data from X=0 to X=Dw-1 are stored in the memory in sequence.

③The Bw scan line moves downward one line, and steps ① to ② are repeated until Y0 moves to the Sw-1 line.

④Data organization is completed.

Display areas B, C, and D organize display data according to the data organization method of A. The organized display data blocks are stored in RAM0 in the order of A, B, C, and D, and then the display data blocks A, B, C, and D in RAM0 are copied to RAM1 in the order of B, C, D, and A. The display data of any two adjacent display blocks have the same address storage area in the two RAMs. The corresponding relationship between the display data and the memory of RAM0 and RAM1 is shown in Figure 2.

Scan group 1 is from Y0=0 to Y0=Sw-1, corresponding to display block A, the data has been organized and stored in the memory, and the display data can be directly output; scan group 2 is from Y0=Lh to Y0=Lh+ Sw-1, and the corresponding display block B has also been organized and can be directly output. However, the position of scan group 3 is unusual, and its scan lines correspond to two blocks A and B respectively; the Oth, 1st, ..., Bw-1th scan lines correspond to the 1st, 2nd, ..., Bw-2th of scan group 1 of display block A respectively; and the Bw-1th scan line corresponds to the Oth scan line of scan group 2 of display block B. If the screen data corresponding to scan group 3 is to be displayed on the display screen, the display data organized by the 1st, 2nd, ..., Bw-1th scan lines of scan group 1 and the Oth scan line of scan group 2 must be used as output data at the same time. Since the display data of display blocks A and B are organized separately, D0, D2, ..., DBw-1 of RAM0 and D0 of RAM1 are used as Bw bits of data output to the display screen. This requires selecting the required Bw bits from the 2Bw bits output simultaneously by the two RAMs
as output data, and these Bw bits of data are continuous.

Display steps (only the vertical movement display effect is considered here); when the dual RAM technology outputs the display data, the two data with the same address in the two RAMs are output simultaneously. Therefore, if RAM0 is set as the main memory and RAM1 is set as the slave memory, when the display data of the two RAMs are stored in a serial memory, the even address unit should store the data of RAM0, and the odd address unit should store the data of RAM1. Since the data width is 8, 16 bits of data are output each time. If the (XL, YL) point in the display area is used as the display starting point, and a screen of display information is displayed on the LED screen , then its data selection control bit is only related to YL, scan line and scan width Sw. The starting row coordinate of the display area is YL, and a display area has Bw & mid dot;Sw rows, then the block where YL is located is:

It is not very meaningful to discuss the coordinates of YL in the actual display area here. We only need to pay attention to the relative coordinates of YL in the current display block. NL=YL%(Bw·Sw) is the relative vertical coordinate of YL in the current display block, and the relative coordinates are (NL, YL). The basis of dynamic display is static display. Static display is characterized by displaying a screen from a specific line. When the display screen starts to display information from the YLth line, because a display area has Sw·Dw data, the starting address of the data displayed in the block where YL is located is:

A display area is divided into Sw areas, and the area where YL is located is recorded as:

One area stores Dw display data, so the relative offset address between the partition address where YL is located and the starting address of the block where it is located is (YL%Sw)·Dw. Therefore, as long as the starting row coordinates of the display information are known, the storage address of the display data in the memory can be obtained.

NL=YL／(Bw·Sw), where i=NL／Sw(0≤i≤7), indicates the number of data bits that need to be selected when the display information spans two data blocks. After the memory outputs 16 bits of data [D0, D1, ..., D15], the Di bit is used to control the selection of continuous 8 bits of data [Di, Di+1, ..., D7, ..., D7+i] to be output to the display screen. When the data is output 16 bits starting from the Di bit of a byte, such as [Di, Di+1, ..., D7, ..., D15, D0, ..., Di-1], the first 8 bits are redundant data in the current display, and the following 8 bits of data [D8+i, ..., D15, D0, ..., Di-1] are exactly the 8 bits of data to be output to the display screen. When these 16 bits of data are serially output to an 8-bit shift register, the shift register can just accommodate the upper 8 bits of data and output them for display. The same is true for the output of each column of data afterwards, and no additional instructions or circuits are required to select and output the output data. Before the data of the first column of each row is output, the microcontroller simulates i clock pulses to output to the memory, so that the output data is misaligned and the data is output from the Di position. In addition, when the display information happens to be a block among the A, B, C, and D blocks, there is no need to generate simulated pulses to select the data, but the data is directly output and displayed. Through analysis, it can be seen that the SPI module just has this function. By simulating i clock pulses additionally by the microcontroller and outputting them to the clock signal end of the serial memory, the data can be misaligned and output from a specified position Di. When the display information crosses the Sw-1 interval, if a display has not been completed, the memory address should return to the starting address of the block where YL is located, and the display data should be output from the starting address, and the number of pulses i simulated by the microcontroller will also change accordingly.

2. LED display control system design

LED display control circuit. In order to improve data output efficiency, RAMtron's VRS51L3074 microcontroller with SPI function module is used. VRS51L3074 has a clock frequency of 40 M-Hz, short instruction cycle, fast processing speed and high efficiency; the operating voltage is around 3.3 V, but it is compatible with 5 V. SST25VF016B is an 8-pin serial Flash with SPI interface . 7 4LSl64 is a shift register.

2.1 SPI Function Module of VRS51L3074

The SPI clock frequency of VRS51L3074 can be between SysClk/2 and SysClk/10.

24, the SPI clock frequency can reach up to 20MHz. When VRS51L3074 is used as SPI master, SPI operation control, configuration and status monitoring and other working environments can be set.

Configuration register SP IC ONFIG: mainly sets the chip select signal control mode and SPI interrupt.

Status register SPISTATUS: Mainly used to monitor the SPI operating status.

Transfer word length register SPISIZE: Set the transfer word length. This article sets it to 16 bits, which means 16 bits of data are output each time.

Control register SPICTRL: Set the SPI clock rate, clock phase/polarity, chip select signal, and SPI clock frequency.

Data registers SPIRXTX0~SPIRXTX3: used to access the 32-bit transceiver buffer of the SPI interface. Writing to the data registers is to send data to the transmit buffer, and reading from the data registers is to retrieve the received data from the receive buffer. The transmit and receive buffers of the SPI interface both use a double buffer structure to reduce data conflicts and improve data transmission efficiency from the hardware. Writing to the SPIRXTX0 register in master mode will start SPI transmission. When the length of each line of the transmission word is greater than 8, the SPIRXTX0 register should be written last.

After inputting control signals and data addresses to the serial Flash, the serial Flash data transmission is started, and the display data is output under the SPI clock drive . In addition, the microcontroller can be used to simulate the serial Flash clock signal to control the output of any bit of data.

2.2 Data selection control circuit

The LED display control system is shown in Figure 3. The VRS51L3074 microcontroller has an accurate 40 MHz oscillator inside, and does not require an external crystal oscillator circuit to provide the system clock. The data display uses the SST25VF016B with a memory of 16 Mb. When the dual RAM technology outputs display data, the two data with the same address in the two RAMs are output at the same time. Therefore, when the display data of the two RAMs are stored in a serial memory, the even address unit should store the data of RAM0, and the odd address unit should store the data of RAM1. When the data is output, 16 bits of data are output each time. The operating voltage of the serial memory and the microcontroller are both around 3.3 V, but the VRS51L3074 is compatible with 5V, which simplifies the control circuit. When the control signal and display data are output to the register 74LS164 and the display, 74LVC07 is required for level conversion.

The process of the control system controlling the display data output is:

① Send the scan line address to the LED display through the lower 4 bits of the P2 port.

② By displaying the position of the data in the display area, the address of the display data in the memory is calculated, and the number of bits i selected by the data is calculated.

③ Through the single-chip microcomputer P3.0 port, simulate the shift pulse and output it to the serial Flash clock signal. The number of shift pulses is determined by the number of data selection bits i. This causes the output data to be misaligned and the output display data is correctly selected.

④ Start SPI to read display data, and set the SPI transmission word length to 16 bits. The analog pulse has been output to the serial Flash, causing the data to be misaligned. The 16-bit data [Di, Di+1, ..., D7, ..., D15, D0, ..., Di-1] is output, and the data output to the display [D8+i, ..., D15, D0, ..., Di-1] is in the upper 8 bits, which can be stored in the shift register after shifting. After the first data of each row is output, the data of each column of this row is directly output.

⑤After the 16-bit data is output, an SCK pulse is generated through the P3.1 pin to shift the data output in the shift register 74LSl64 into the serial shift register 74HC595 of the unit board.

⑥ Repeat steps ④ to ⑤ until a row of data is completely output. P3.2 generates an RCK pulse, the read row of data will be output and displayed, and then the scan line moves down one row.

⑦Repeat steps ① to ⑥.

This circuit has the following features: after the display data is output from the serial Flash, it is directly output to the shift register 74LSl64 in DMA mode without being processed by the single-chip microcomputer, and serial-to-parallel conversion is realized at the same time, which not only saves data processing time but also improves display efficiency. Before each field of data is output, the data selection bit i is calculated by the address of the information in the display area, and
i pulses are simulated and output to the serial Flash through the P3.O port , i bits of data are shifted out, and the data is misaligned, so that the output display data can be directly stored in the shift register in the high 8 bits of the 16-bit output data and output to the display screen. In the future, when the display data of each column in the same row is output, there is no need to judge the data selection bit, and the display data is directly output from the memory to the display screen.

The memory efficiency analysis is listed in Table 1.

As can be seen from Table 1, the use of dual RAM technology for output display greatly improves memory efficiency and reduces the occupancy of display data memory. When the amount of displayed information is large, dynamic data organization uses more memory and has low utilization, and the use of dual RAM technology just solves this problem. The memory efficiency of one RAM (static display) is 100%, and the efficiency of dual RAM is 50%. When there are N RAMs, the efficiency is (N-1)/N.