NiosII I2C Control IP and Its Application in Imaging System

1 IP hardware structure and registers

1.1 IP Hardware Structure

The internal structure of the IP is shown in Figure 1. It is mainly composed of five modules: baud rate clock register, register group controller, parallel I/O interface , I2C programmable interface, and I2C interface engine.

The baud rate clock generator is used to generate the basic clock frequency for the I2C IP to work; the register group controller is used to set the registers, and the setting data is transmitted to the module through the parallel I/O interface; the parallel I/O interface module is used to process the commands transmitted by the programmable interface module; the I2C programmable interface module is used to set the addresses of each register of the IP; the I2C interface engine module executes the data transmission on the I2C bus .

1.2 Register Structure

The I2C control IP is mainly composed of 6 registers, as listed in Table 1. By reading and writing registers, the transmission of I2C bus data can be easily controlled, thereby realizing the communication between the NiosII processor and the device. The data register is used to store the data to be transmitted on the I2C bus; the baud rate generation module, the baud rate clock register and the clock register jointly determine the frequency of SCL on the I2C bus. The calculation formula of SCL is where System_clk is the system clock; Value is the value of the clock register; divider is the frequency division number corresponding to the value of the baud rate clock register (the difference between the register value and the frequency division number is 1. If the register is set to 0, the frequency division number is 1; if the register is set to 1, the frequency division value is 2).

Detailed introduction to local address register, control register and status register is omitted - Editor's note.

2 Application of I2C Control IP in Imaging System

In imaging systems, C MOS sensors are widely used. Most of these sensors have built-in I2C serial communication interfaces. This article takes MT9M011 as an example to introduce the application of I2C control IP in imaging systems. MT9M011 sensors can be divided into two modes according to the number of read and write bits: 16-bit data read and write mode and 8-bit data read and write mode. Here, the exposure register is selected and the 16-bit read and write mode is used for operation. The timing is shown in Figure 2.

The upper 7 bits of the slave device address (write mode) and the slave device address (read mode) are the slave device address, and the 8th bit is the read/write control bit (R/W), which controls the direction of data transmission.

Write data to the exposure register 0x09: The master device starts the transmission and then sends the address of the slave device it wants to address (write mode). MT9M011 monitors the bus and responds with a one-bit acknowledgement signal when its address matches the transmitted slave device address. Then the master device sends the exposure register address, and MT9M011 responds again. After writing 16 bits of data to the exposure register, the master device stops writing data. Every time 8 bits of data are transmitted, the slave device MT9M011 will generate a one-bit acknowledgement signal.

Reading data from exposure register 0x09: The beginning part is the same as the timing of writing data. After the master device sends the slave device address (write mode) and the register address, it needs to restart and send the slave device address (read mode) before reading data from the register. After reading each byte of data, the master device will generate a 1-bit response signal. When 16 bits of data are read, the master device sends a 1-bit non-response signal and the transmission ends.

3 IP Application Examples

3.1 Hardware Design

This article uses I2C control IP to configure the image sensor MT9M011 register in parallel. The hardware design is based on SOPC technology, integrating the 32-bit Nios II soft-core processor, SDRAM interface module, TIMER timer module (providing the frequency of signal sampling in SignaltapII), PIO module and I2C control IP (configured as a master device) provided by the system component library into an FPGA . QuartusII top-level principle is omitted - Editor's note.

3.2 Software Design

There are two ways to write software: one is to operate the I2C control IP application programming interface (API) function; the other is to use the read and write functions provided by Altera to operate the register. In order to improve the speed of system operation, the second method is adopted. The system software part is completed by writing C code in NiosII IDE.

The parallel configuration procedure for CMOS registers mainly includes the following two parts:

①IP initialization settings: including setting the baud rate, setting the local address register, and setting the clock register value.

② Select CMOS1 to read and write its register; select CMOS2 to read and write its register. Register selects exposure register.

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The key codes are as follows:

The checkBus function queries the status register to determine the busy/idle status of the I2C bus, and the checkProgres function queries the status register to determine whether the bus data has been transferred. In order to observe whether the read data is consistent with the written data, the program is usually included in a while statement.

4 Experimental Verification

Burn the download file generated by the hardware system to the FPGA chip and run the C code program. Use the SignahapII logic analyzer that comes with QuartusII to observe the data on the I2C bus. Figure 3 shows the obtained waveform. The signals from top to bottom are the I2C bus signals m_sclk_2, m_sda_2, m_sclk_1, and m_sda_1 on CMOS2/CMOS1. The first half writes 0x06 and 0x07 to CMOS1 and then reads it out; the second half writes the same number to CMOS2 and reads it out. This waveform meets the timing read and write requirements of the MT9M011 image sensor.

5 System Expansion

In applications that require multi-channel CMOS configuration, the I2C control IP can be used to easily implement multi-channel parallel CMOS register configuration. For example, an 8-channel parallel CMOS configuration system: 8 CMOS sensor chips are soldered on the circuit board, and the enable is loaded in parallel to the 8 CMOS chips by controlling the 3-channel signal of the distributor . The 3-channel control signal and the enable signal are realized by controlling the PIO interface module of the SOPC system, and the transmission of the configuration data is completed under the control of the I2C control IP. The circuit board structure is simple and the system is easy to implement.

Conclusion

The I2C IP introduced in this article can be loaded into the SOPC system as a custom component, making the system design more flexible and having great potential for functional expansion. In the imaging system using CMOS image sensor, the I2C interface is widely used. This article gives an application example of the IP to illustrate that the use of the IP has broad prospects and high application value.