The AI ​​chip race has just begun, but the future belongs to only a few players

There are many players in the field of AI chips, and their products are constantly being updated and iterated. However, so far, there are very few AI chips that fully meet the description and benchmarks. Even Google's TPU is not enough to support the long-term development of AI.

The rise of artificial intelligence has three basic elements: algorithms, data, and computing power. As cloud computing is widely used and deep learning becomes the mainstream method of AI research and application, AI's requirements for computing power are rapidly increasing. The continued development of AI chips is an unremitting pursuit of computing power.

There are many directions for AI chips, and companies focus on the "primary" track

Currently, driven by Moore's Law, CPUs can provide the required computing performance for artificial intelligence within a reasonable computing power, price, power consumption and time. However, many data processing of AI involves matrix multiplication and addition, and the design and optimization of CPUs are for hundreds of tasks. Therefore, using CPUs to execute AI algorithms, a large amount of other logic inside them is completely wasted for current AI algorithms, and the CPU cannot achieve the best cost-effectiveness. In the face of explosive computing needs, general-purpose chips will be even more unsustainable.

Therefore, AI chips with massive parallel computing capabilities and the ability to accelerate AI computing have emerged. Faced with the increasing number of B-side application scenarios, more and more AI chip companies are joining the competition.

In fact, the research and development of AI chips has two different directions: first, adding dedicated accelerators to the existing computing architecture, namely "AI acceleration chips", which deterministically accelerate a certain type of specific algorithm or task, thereby meeting the target application field's requirements in terms of speed, power consumption, memory usage, and deployment cost.

Second, completely redevelop and create a new architecture that simulates the human brain neural network, namely the "smart chip". It allows the chip to use different AI algorithms to learn and deduce like humans, handle a series of tasks including perception, understanding, analysis, decision-making and action, and have the ability to adapt to changes in scenarios. At present, there are two design methods for this type of chip: one is the "neuromorphic chip" based on brain-like computing; the other is the "software-defined chip" based on reconfigurable computing.

"Smart chips" are still in the early stages of development and are not suitable for commercial applications. Therefore, the main method currently adopted by companies is to add artificial intelligence accelerators to the existing computing architecture. The research and development of AI acceleration chips is also divided into two main ways: one is to use existing GPUs, multi-core processors, DSPs, and FPGA chips to optimize software and hardware; the other is to design dedicated chips, that is, ASICs.

GPU, FPGA and ASIC have become the mainstream of the current AI chip industry. Among them, GPU is the most mature and widely used general-purpose chip for AI computing on the market. It is a large-scale parallel computing architecture composed of a large number of cores and is designed for processing multiple tasks simultaneously. The GPU desktop and server markets are mainly divided by NVIDIA and AMD, while the mobile market is dominated by many companies such as Qualcomm, Apple, and MediaTek.

ASIC is a custom chip designed for a specific purpose and for specific user needs. It has strong performance, small size, low power consumption and high reliability. In the case of large-scale mass production, it also has the characteristics of low cost. In recent years, more and more companies have begun to use ASIC chips to accelerate deep learning algorithms, among which TPU is the most outstanding. This is a special chip for artificial intelligence accelerators fully customized for machine learning by Google to improve AI computing power while significantly reducing power consumption. Its performance is very outstanding. In addition, the Cambricon series of processors developed by the domestic enterprise Cambricon have also attracted widespread attention. The global market size of ASIC has grown from US$16.3 billion in 2012 to US$25.7 billion in 2017. It is expected to maintain an annual compound growth rate of 18.4% in the next five years, reaching US$59.7 billion by 2022. At present, the market structure is still relatively fragmented.

FPGA integrates a large number of basic gate circuits and memories, and its flexibility lies between general-purpose processors such as CPUs and GPUs and application-specific integrated circuits ASICs. my country has just started in this area, and there is a huge gap between the four FPGA giants Xilinx, Intel, Lattice, and Microsemi. In terms of market share, Xilinx and Intel together account for about 90% of the market, of which Xilinx accounts for more than 50%. In 2017, the global market size of FPGA was US$5.96 billion, and it is expected to reach US$9.80 billion by 2023.

The development of AI is still in its infancy, and AI chips are mainly moving in the direction of "AI acceleration chips". The development of artificial intelligence computing generally needs to go through three stages: traditional intelligent computing, intelligent computing based on deep learning, and intelligent computing based on neuromorphism. As for neuromorphic chips for the third stage, few companies are currently involved. There is still a long way to go before it becomes mainstream in the future. However, Intel has demonstrated Loihi at the 2018 International Consumer Electronics Show, a new type of neuromorphic computing chip based on 14nm, with a heterogeneous design, consisting of 128 Neuromorphic Cores + 3 low-power Intel X86 cores, claiming to have 130,000 neurons and 130 million synapses.

The AI ​​chip market is huge, but may not be able to accommodate a large number of players

According to Gartner's forecast data, the global artificial intelligence chip market size will soar in the next five years, growing from US$4.27 billion in 2018 to US$34.3 billion, an increase of more than 7 times. It can be said that the AI ​​chip market will have a lot of room for growth in the future.

However, for many start-ups, developing chips will face huge challenges in terms of time and money. In terms of time, it usually takes about two years for chip development to go from project establishment to market launch. In comparison, the more important point is that the cost of chips is very high.

In the field of artificial intelligence applications, different processes are used depending on the deployment location and task requirements of the chip. In general, chips for terminal devices often use 65nm and 28nm processes; chips for edge devices and some mobile devices are basically 16nm or 10nm; and cloud chips are usually 7nm.

The chip manufacturing process determines the development cost. According to IBS's estimated data, the development cost of a 65nm chip is $28.5 million, and the development cost of a 5nm chip is $542.2 million, depending on the manufacturing process. Therefore , in chip R&D, the tolerance for errors is almost zero . At present, the more mature ones are the 40nm and 55nm processes, and for the current advanced 7nm process, the technology of many companies is not mature enough.

Due to the high development costs and the development cycle that takes years, AI chip companies need a lot of capital injection in the early stages of financing to survive the period when there is no product sales. Government subsidies and investor funds tend to favor companies with good sales performance. The capital market also hopes for a shorter investment cycle. Therefore, financing has become a threshold.

In addition, since the chip development cycle usually takes 1-3 years, the software will develop very quickly in normal times, but the algorithm will also be updated rapidly during this period. How the chip supports these updates is also a difficulty.

In the long run, the technological development of AI chips themselves will face the following difficulties.

The mainstream AI chip currently uses the von Neumann architecture. In the von Neumann architecture, the chip adopts a 1-in, 1-out method in computing. Data is extracted from the memory outside the processing unit, and written back to the memory after processing. The task is completed by reading in sequence. Due to the speed difference between the computing components and the storage components, when the computing power reaches a certain level, the speed of accessing the memory cannot keep up with the speed at which the computing components consume data, and adding computing components cannot be fully utilized. This is not only a bottleneck in the implementation of AI chips, but also a problem that has long plagued computer architecture.

In addition, to meet the computing power required for the development of artificial intelligence, it is necessary to reduce the integrated size in the CMOS process and continuously improve the system performance of the chip. Today, 7nm has begun mass production, and the technical definition of the 5nm node has been completed. However, this has also created bottlenecks in CMOS processes and devices. First, because the energy consumed by nanoscale transistors is very high, it is very difficult to achieve dense chip packaging. Secondly, a CMOS device of a few nanometers has a layer thickness of only a few atomic layers. Such a thickness can easily lead to current leakage, and the effect of process size reduction will also be affected.

Although the AI ​​chip market has a lot of room for growth, it may not be able to accommodate enough companies. The characteristics of the industry itself and the current stage of development of AI have determined that AI chip companies will have a relatively long period of setbacks, and in the process, the bubble created by capital will also be compressed.