Design of a Fault Monitoring System for a Test Equipment

Design of Fault Monitoring System

For the test equipment and a control system, they are connected by cables. The test equipment sends control signals to the control system, sends data, and receives status signals returned by the control system through cables. Therefore, the working status of the comprehensive test equipment and the control system in each test step is reflected in these cables. To this end, this paper proposes an overall design scheme as shown in Figure 1.

Figure 1 Overall system design

In terms of equipment connection, the fault monitoring and diagnosis system is connected to the control system and the comprehensive test equipment through the signal transfer box. When the test equipment performs comprehensive tests on the control system, the signal transfer box transfers the various signals generated by the control system and its comprehensive test equipment and sends them to the signal conditioning unit, which completes the signal filtering, limiting, shaping, amplification, isolation and other processing. At the same time, the PC104 computer sends control instructions to the data acquisition board through the PC bus, controls the corresponding relay group and analog switch to work, connects the signal channel that needs to be collected, collects the voltage, frequency, switch and time of the equipment under test through the A/D interface board and the I/O interface board, and analyzes, judges and displays the collected signals.

In view of the fact that the monitoring signals of the test equipment are of many types and large quantities, combined with the structural characteristics of the embedded CPU motherboard and data acquisition board based on the PC104 bus, the system adopts the mature PC104 bus CPU module PCM3350, I/O interface board ONYX.MM-XT and A/D interface board DIAMOND-MM-AT as the development platform, plus the self-developed peripheral signal conditioning circuit and interface module, and uses modular design ideas to realize the functions required by the fault monitoring and diagnosis system.

Design of switch quantity measurement module

There are 50 switch signals that need to be collected in this system. Their normal state is low level (amplitude is 0V) and they are high level when working. Among them, 19 signals have a high level of 15V and 31 signals have a high level of 5V.

Isolation circuit design

The isolation test and level conversion function of the system are mainly realized by the optoelectronic isolation chip TLP521-4L. Considering the limited driving ability of the digital signal introduced by the human, in order to reduce the impact of the monitoring and diagnosis system on the work of the integrated test equipment and enhance the driving ability of the signal, the switch signal to be tested needs to be input into the eight-input/output inverting driver ULN2803A before the signal is optically isolated to ensure that TLP521-4L can work stably and reliably. The designed switch signal optoelectronic isolation circuit is shown in Figure 2.

Figure 2 Switch signal acquisition circuit

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Switching signal acquisition

For the 31-way switch quantity with a high level state of 5V, after being optically isolated by the circuit of Figure 2, they are respectively connected to the A port, B port and C port on the expansion 82C55#3 board and the C port of 82C55#2 on the ONYXˉMM-XT board.

For the 19-way switch signal with a high level state of 15V, due to the high voltage, it needs to be divided by a 1MΩ and a 510kΩ resistor, and then introduced to the 1.2L input end of the optoelectronic isolation chip TLP52 after the voltage follower follows the signal and the ULN2803A reverse drive. When the monitoring and diagnosis system needs to collect data, the PC104 computer sends control instructions to the three 82C55 chips through the PC bus, reads the corresponding digital acquisition channel, and realizes the acquisition of the switch signal. The designed switch signal acquisition circuit is shown in Figure 2.

Design of voltage measurement module

Design of voltage divider circuit

After analysis and summary, it is found that when the test equipment is working, the voltage and resistance state parameters of each functional module can be fully monitored by detecting its 64 voltage signals. The measurement principle of the resistance value is still to measure the voltage. A standard voltage % first passes through a known resistor R., and then is connected in series to the measured resistor Rx, so only the voltage on the resistor % needs to be measured. According to Ohm's law:

Therefore, the value of the measured voltage RX is:

Among them, U0 and R0 are known, UX is the measured voltage, so it is easy to calculate the value of by formula (2).

Since DIAMOND-MM AT requires the voltage signal input range to be -10V to +10V, and the voltage signal range of the test equipment is 0 to 170V, in order to ensure the normal operation of the A/D converter, the input voltage signals of different amplitudes need to be adjusted to the range of 0 to 10V, so the voltage signal greater than 10V needs to be attenuated. To achieve voltage attenuation, a resistor divider network is usually used. The voltage attenuation of the voltage divider circuit is the ratio of the output voltage Ui\' to the input voltage Ui. Assuming that the parallel impedance of R2C2 is Z2 and the parallel impedance of R1C1 is Z1, when the attenuator component parameters satisfy the relationship of R1C1=R2C2, the influence of the distributed capacitance can be ignored. At this time, the voltage divider ratio of the attenuator is:

The voltage value input to the A/D converter is:

In order to reduce the impact on the measured signal, R2 and R1 are usually set to larger values, but the value of the A/D input impedance R is not infinite, so the actual input voltage to the A/D converter is:

in:

From equations (5) and (6), it can be seen that if the input impedance value Ri of the A/D is close to R2, it will cause a large error in the measurement result. The solution is to add a voltage follower between the voltage divider network and the A/D converter. Since the input impedance of the voltage follower is very large, R, is approximately infinite, so the influence of R, on the measurement result can be ignored. The improved voltage divider network circuit is shown in Figure 3.

Figure 3 Improved voltage divider network

In order to reduce the error caused by resistor voltage division, the voltage division resistors in the circuit are uniformly made of metal film resistors with an accuracy of 1%. After the follower is isolated, the influence of the sampling circuit on the original signal is reduced to the minimum.

Isolation of voltage signals

Considering that the voltage signal requires measuring its amplitude, it is not possible to use the isolation switch signal method to achieve voltage signal isolation. This system uses the high-speed coupled isolation amplifier AD215 chip produced by Meiffino to achieve linear isolation of voltage signals. Design + AD215 is mainly used to achieve signal isolation, so its amplification factor is set to 1:1. [page]

Voltage signal measurement

Although the test equipment has many voltage paths to be tested, the voltages generated are all sequentially executed signals. Considering the high cost of linear optical isolation AD215 and A/D board DIAMOND-MM AT, in order to reduce development costs, simplify circuit design and reduce the size of the circuit board, this monitoring and diagnostic system uses multiplexing technology, so that the A/D board can measure multiple signals using a single A/D measurement channel. After the A/D converter collects one channel, the PCM3350 sends instructions to control the analog switch action, switches to another channel and collects, and then switches to the next channel, and so on. The collection principle is shown in Figure 4.

Figure 4 Principle block diagram of voltage signal acquisition

Design of time measurement module

According to the working conditions of the test equipment, the maximum timing required by this monitoring and diagnostic system should be 3s, while the maximum timing time of a 16-bit timer with a 4MHz clock is only 16 384ms. Therefore, when measuring time, two 16-bit counters need to be cascaded into 32 bits to work, so that the maximum timing time of the timer can reach 1073.742s. In hardware design, the system cascades counter 1 and counter 2, that is, OUT1 of counter 1 is connected to CLK2 of counter 2. The gate signals GATE1 and GATE2 are controlled by the BS port of 82C55#2 on the ONYX-MM-XT board, and CLK1 is terminated with a standard frequency source with a frequency of 4MHz. By setting the initial count value of counter 2 and reading its count value after the count is completed, the measured time can be calculated using a certain conversion relationship. The measurement principle is shown in Figure 5.

Figure 5 Schematic diagram of time signal measurement

Design of frequency measurement module

Timing Implementation

Since the standard input clock frequency of the ONYX-MM-xr board is 4MHz, and the signal frequency that the system needs to measure is 3KHz, the measurement of this frequency is a measurement of timing 8254 for 0.01s and counting the signal for 30. The count value of the timer is:

The design is still to cascade counters 1 and 2 as a timer according to Figure 8, and trigger interrupt INT7 every 0.01s. The working mode is set as follows: counter 1 works in mode 2, and counter 2 works in mode 0. Assume that the initial count value of counter 1 is NI, and the initial count value of counter 2 is N2. As long as N1×N2＝40000, then send the initial count values ​​to the corresponding registers, turn on the gate signal and start the counter to achieve timing.

Frequency measurement implementation

According to the design requirements of the system and the characteristics of the measured frequency signal, the working modes of each counter are set as follows: counter 0 works in mode 4, counter 1 works in mode 2, and counter 2 works in mode 0. Among them, the CLK0 terminal of counter 0 is connected to the measured frequency as an event counter, the CLK1 terminal of counter 1 is connected to the standard input clock frequency f0 of 4MHz, counter 1 and counter 2 form a series structure as a timer, and GATE0, GATE1 and GATE2 are all controlled by the BS port of 82C55#2. In this way, the value of the measured frequency can be calculated by the following formula:

Wherein, N0 is the current count value of counter 0, and OxFFFF is the initial count value of counter 0. The principle of frequency signal measurement is shown in FIG5 .

in conclusion

By conducting an online power-on test on the fault monitoring and diagnosis system and the test equipment and analyzing the measurement results for multiple times, the results show that the parameter values ​​actually measured by the system are very close to the standard parameter values ​​of the comprehensive test equipment, which meets the needs of monitoring various parameters of the test equipment and achieves the design index requirements of the test equipment fault monitoring and diagnosis system.