Design of Cable Fault Detector Based on Pulse Reflection Method

Introduction
Cables are important carriers for signal transmission in communication, testing and other systems. With the increase in the number of cables and the extension of their operating time, cables are also failing more and more frequently. The concealment of cable lines and the limitations of test equipment make it very difficult to find cable faults. This paper designs a cable fault detector with the embedded microprocessor Nios as the core. A/D devices and FPGA are used to form a high-speed data acquisition system with variable frequency. The principle of low-voltage pulse reflection method is used to detect and locate the break, short circuit, break point and short circuit point of the cable. The instrument can be widely used in communication maintenance, engineering construction and integrated wiring, and test and maintain various cables such as local telephone cables and coaxial cables.

1 Overall structure of the system
The low-voltage pulse reflection method is used to detect cable faults. The main principle is: send a voltage pulse to the cable. When the transmitted pulse encounters a fault on the transmission line, a reverse pulse is generated due to the mismatch of the impedance at the fault point. The time difference △T between the two is calculated, and the characteristics of the reflected pulse are analyzed to characterize and locate the fault. This method is suitable for testing broken wires, poor contact, low resistance or short circuit faults.
The distance L of the fault point is: L=V·△T/2. In the formula, V is the propagation speed of the pulse in the cable. The nature of the fault can be judged according to the polarity of the reverse pulse: the reverse pulse caused by broken wire or poor contact is positive, and the reverse pulse caused by low resistance or short circuit fault is negative.
The instrument is a portable cable fault detection device that can use modern electronic technology (such as high-speed A/D technology, asynchronous FIFO technology, field programmable logic array FPGA, etc.) to improve integration and flexibility. The overall structure of the system is shown in Figure 1.

The pulse generation circuit generates the detection pulse, and the high-speed A/D converter samples the pulse and its reflected echo signal, using the asynchronous FIFO as the cache of the A/D sampling data. The soft-core Nios is the core of the system, controlling the start and end of the detection task, the selection of the pulse sending and receiving mode, the processing and calculation of the A/D sampling data, the judgment and display of the fault nature and location, etc. Among them, the soft-core processor and the logic function are programmed in the field programmable logic device.

2 Functions and performance indicators
Short circuit test: Detect whether there is unnecessary connection between the cable cores and their location.
Open circuit test: Detect whether a core wire in the cable is open circuit and its location.
Display: Display the test results, that is, the location of the open circuit and short circuit in the measurement.
Measurement range: 2 to 1000 m.
Test accuracy: Two accuracy options of 2 m and 10 m are available.
Pulse amplitude: 5 V with open load .
Pulse width: 20 ns, 100 ns.
Maximum sampling rate: 100 MHz.
Waveform record length: 1024 points. [page]

3 Hardware Design
Using Altera's Cyelone II series FPGA device EP2C20 as the core, the microprocessor was designed using its Nios soft core function, and the design of related circuits was completed. By programming the FPGA device to customize the pulse generation, high-speed clock, and high-speed data storage FIFO modules, the pulse sending and receiving circuits and high-speed data acquisition and processing circuits were designed based on this.
3.1 Microprocessor System
In simple terms, Nios is a processor IP core that designers can put into FPGA. The Nios soft core processor is a general-purpose microprocessor with a reduced instruction set of the basic pipeline, and the clock signal frequency can reach up to 75 MHz. Flash is used to store the startup code and application program. When the system is reset or powered on, the startup code in the Flash will be executed. SDRAM is used to store the executable code and data of the application program to provide running space for the program. The design of the connection between the Nios soft core and Flash and SDRAM in FPGA is shown in Figure 2.

3.2 Generation of detection pulses
The width of the pulse signal used for fault detection is 20 to 100 ns. The working clock of FPGA can reach 200 MHz. The subtraction counter generated in it can generate a pulse signal that meets the pulse width requirement. The amplitude of the pulse generated by the subtraction counter is limited by the working level of FPGA, which is not enough for detection. Therefore, the square wave pulse coming out of FPGA needs to be amplified before it can be coupled to the detected cable. The pulse signal conditioning circuit is shown in Figure 3. SN74LVC4245A is used for level conversion. Both sta and pulse_input come from FPGA.

This design uses a 5 V pulse amplitude, and the pulse is fed by a transistor emitter drive, which is relatively simple and applicable to a wide range of devices.

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3.3 A/D conversion circuit
The width of the detection pulse is 20-100 ns, and the corresponding data sampling rate varies between 20 MHz and 100 MHz. It is difficult for general A/D chips to meet the sampling requirements, and it is difficult to use multiple A/D chips in terms of cost and design. Here, ADC08100 from NS Company of the United States is selected, and its sampling rate is 20-100 Msps. At this time, the power consumption of sampling is 1.3 mW/Msps. The power consumption of sampling will increase with the increase of sampling clock, but the sampling characteristics will not be affected. Therefore, in a system with various sampling rates, one chip can play the role of multiple chips. According to the different sampling rates, a clock control module generates a corresponding sampling clock signal, so that the chip works at the required rate, which can save costs and simplify the design. ADC08100 and FPGA can be used together to easily change the sampling clock, which has great flexibility. The
A/D conversion circuit is shown in Figure 4. The detection pulse and echo signal need to be converted into a signal suitable for the voltage level of the A/D chip before sampling. The pulse is clamped before inputting into the operational amplifier by using two sets of inverted diodes in parallel to prevent the pulse from being too high and breaking through the operational amplifier.

3.4 Generation of clock signal
The generation of detection pulse, sampling of ADC08100, and data buffering of asynchronous FIFO constitute a high-speed A/D data acquisition system. This has high requirements for the timing coordination of various signals, and requires a special clock unit to coordinate so that the circuit works in the correct timing. In FPGA, the clock module can be easily customized to generate A/D sampling clock, asynchronous memory read and write clock, and pulse generation module count clock. All clocks are synchronized by a high-speed clock, and the entire system runs synchronously under the same start signal, thereby ensuring the sampling timing requirements.
3.5 Power supply module
The system contains both analog circuits and high-speed digital circuits, and the types of power supplies used are complex, with multiple power supply signals such as +5 V, +3.3 V, +1.2 V, and -5 V. In the design and production of circuit boards, it is necessary to reduce the electromagnetic interference of high-frequency digital signals on analog signals and avoid interference between various power supplies. Therefore, it is necessary to reasonably plan the module layout and wiring direction to improve signal stability.

4 Software Design
Software design mainly includes FPGA development and application, application design and LCD driver design.
4.1 FPGA development and application
Field Programmable Logic Device FPGA (Field Programming Gate Array) has the characteristics of high density, high speed, low power consumption and powerful functions. In this system, Altera's CycloneII series devices are used to realize high-speed data acquisition and storage functions. The design is completed using the hardware description language VHDL in QuartuslI 7.1 software. The design process of high-density programmable logic devices includes: design preparation, design input, design processing and device programming 4 steps, as well as the corresponding functional simulation (pre-simulation), timing simulation (post-simulation) and device testing 3 design verification processes.
In this design, the design of modules such as Nios microprocessor, pulse generation, high-speed clock and high-speed data storage FIFO is mainly included.
4.2 Application Design
The application controls the start and end of the detection task, the selection of pulse sending and receiving mode, the processing and calculation of A/D sampling data, the judgment of fault nature and location, and the output of results.

Conclusion
This paper proposes a design scheme for cable fault detector based on Nios soft core. For the specific implementation of pulse reflection method to detect faults, a design idea of ​​high-speed sampling system based on field programmable logic device is proposed, and the system is designed comprehensively on this basis. The simulation and test results show that the system can detect cable break, short circuit and other faults, and has the advantages of online monitoring, easy control, and flexible and good expansion function.