Design of a Signal Source for Circuit Board Detector Based on DDS

0 Introduction

The circuit board detector of a certain type of missile test equipment mainly completes the fault detection of the circuit board of the test equipment. The detection system requires the excitation signal generation circuit to be small in size, flexible in configuration, high in accuracy and fast in conversion speed. The FPGA-based DDS signal generator can better meet the requirements of the detector than the traditional signal generator.

Direct digital frequency synthesis (DDS) is a frequency synthesis technology that directly synthesizes the required waveform based on the concept of phase. It is the third generation of frequency synthesis technology developed after direct frequency synthesis and indirect frequency synthesis. It breaks through the principles of the first two generations of frequency synthesis methods and performs frequency synthesis based on the concept of "phase". This method can not only generate sine waves, square waves, and triangle waves of different frequencies, but also control the initial phase of the waveform. It can also be used to generate arbitrary waveforms. It has been widely used.

1 Working principle and basic structure of DDS

A direct digital frequency synthesizer consists of a phase accumulator, an adder, a waveform storage ROM, a D/A converter and a low-pass filter. The principle block diagram of DDS is shown in Figure 1.

In Figure 1, K is the frequency control word, P is the phase control word, W is the waveform control word, fc is the reference clock frequency, N is the word length of the phase accumulator, and D is the word length of the ROM data bit and the D/A converter. The phase accumulator accumulates with a step length of K under the control of the clock, fc, and the output N-bit binary code is added with the phase control word P and the waveform control word W as the address of the waveform ROM to address the waveform ROM. The D-bit amplitude code output by the waveform ROM is converted into a step wave by the D/A converter, and then smoothed by a low-pass filter to obtain the synthesized signal waveform. The shape of the synthesized signal waveform depends on the amplitude code stored in the waveform ROM, so DDS can generate any waveform.

Assume the frequency control word is K, the output frequency is f0, the reference clock is fc, the phase register is N bits, and the frequency resolution is △f, then:

By changing the frequency control word and increasing the number of register bits, a satisfactory frequency can be obtained. [page]

2 Design of DDS signal generator based on FPGA

The signal generator is used as the excitation signal source of the circuit board detector. The generated signals are: sine wave with a frequency of 16,000 ± 0.8 Hz, square wave with a frequency of 128,000 ± 1.2 Hz, 64,000 ± 3.2 Hz, 4,000 ± 0.2 Hz, and pulse signal with a period of 10 μs and a duty cycle of 1:4. The following takes the generation of sine wave as an example to illustrate the implementation process of DDS. When f0 = 16,000 Hz and N = 16, according to formula (1), K = 104.

2.1 Phase Accumulator

The phase accumulator mainly generates the address of the ROM lookup table according to the frequency control word. It is implemented in the hardware description language Verilog DHL. The source program is:

After the text is input, it is compiled with Quartus II, and then a .bsf file is generated for calling in the top-level design. The generated top-level module is shown in Figure 2.

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2.2 ROM Lookup Table

In DDS, the design of waveform memory is a key and important part. The data output by the phase accumulator is used as the address of the waveform memory to convert the phase and amplitude of the waveform, so that the amplitude of the output waveform can be determined at a given time. The N-bit addressing ROM is equivalent to discretizing the periodic signal of 0°~360° into a sequence of 2N sample values. If the waveform ROM has D-bit data bits, the values ​​of the 2N sample values ​​are stored in the waveform ROM as D-bit binary values. According to the different addresses, the values ​​of the sine wave and square wave of the corresponding phase can be output. In this design, N=11 is taken, and 2048 waveform data are stored in the ROM lookup table, with a bit width of 10 bits.

To build a ROM lookup table, you must first generate a .mif file. The specific method is to use Quartus II to create a .mif file, and then fill in this file. Here you need to use Matlab to fill in the .mif file. The specific method is as follows:

(1) First generate the .mif file using QuartusⅡ.

(2) Write the following program in Matlab:

(3) Select the data in the workspace in Desktop, copy the data and paste it into a txt document and save it.

(4) Then copy and paste the data in the txt document into the .mif file created in QuartusⅡ and save it.

The called waveform memory module is shown in Figure 3.

2.3 Establishment of top-level modules

According to the working principle block diagram of the overall DDS circuit, its core is composed of a ROM memory, a phase accumulator, a phase-locked loop and corresponding input and output signals. The ROM lookup table has an input address that is the high 11 bits of the phase accumulator, which is allowed in engineering. The core circuit module diagram of DDS is shown in Figure 4.

The generation of square wave and pulse signals only requires converting the contents of the ROM lookup table into the corresponding waveforms, and a multi-way selection switch is added to the top module of the entire signal source. [page]

3 Waveform Simulation and Hardware Verification

After completing the DDS circuit design, the circuit was functionally simulated, the simulation waveform was displayed through Matlab, and hardware verification was performed through the DE2-70 development board of Altera's CycloneⅡ series chip combined with an embedded logic analyzer.

3.1 Waveform simulation

During the design process of the DDS circuit, functional simulation was performed, as shown in Figure 5. Since the simulation waveform is a digital code, the waveform of the DDS output cannot be seen intuitively. In order to facilitate the debugging of the design circuit, a .tbl file is first generated, and then the waveform curves of the sine wave, square wave, and pulse signal generated by the corresponding Matlab program are shown in Figure 6.

Figures 5 and 6 show the functional simulation waveforms of the sine wave generated by the frequency control word of 68h, the square wave generated by the frequency control word of 346h, and the pulse signal generated by the frequency control word of 27Fh. It can be seen from the functional simulation waveforms that the DDS circuit can well generate the excitation signal required by the circuit board detector. [page]

3.2 Hardware Verification

In order to analyze the DDS circuit more clearly, the DE2-70 development board combined with the SignalTapⅡ embedded logic analyzer is used to perform real-time hardware verification of the design. First, some modifications are made to the DDS top-level circuit diagram, mainly to set the pins. Download the modified top-level file to DE2-70, and observe the FPGA output waveform in real time through the SignalTapⅡ embedded logic analyzer, as shown in Figure 7. The time length of the measured signal that SignalTapⅡ can display is T, and the calculation formula is as follows:

Where: N is the number of sampling points stored in the buffer of SignalTapⅡ, and Ts is the period of the sampling clock of SignalTapⅡ. From Figure 7 and formula (3), we can get the conclusion shown in Table 1.

There are two main reasons for the error. One is the truncation error. The address input of the ROM lookup table is the upper 11 bits of the phase accumulator. The other is the error introduced by the quantization of the sine wave. Quantizing the sine signal into a binary number will inevitably cause errors.

4 Conclusion

Through the functional simulation and hardware verification of the DDS circuit, it can be seen that DDS can effectively generate the required waveform signal. Compared with traditional signal generators, it can reduce the size, reduce power consumption, improve reliability and flexibility, and shorten the development cycle, which has high practical value.