IDDQ test process and function implementation based on 2600 series

Test introduction

This test involves measuring the VDD supply current draw of a CMOS IC with the input at VDD or VSS and the output unconnected. Figure 1 is a block diagram of a CMOS inverter test setup. In this example, the 2601/2602 are used to source the voltage (VDD) and measure the resulting quiescent current.

Figure 1. Measuring the quiescent current of a CMOS inverter

Although this example shows an IC with only one gate, many ICs have thousands of gates. Therefore, a predetermined series of test vectors (i.e., a pattern of logic 1s and 0s applied to the input) is typically used to reduce the number of quiescent current measurements, and it is necessary to ensure that all gates are switched or that all required IC logic states are tested.

Applying a constant voltage to the VDD pin of the IC throughout the test keeps the IC in working condition. A good CMOS device draws high current from the VDD supply only when switching; the current consumption under static conditions is extremely low. Depending on the type of defect involved, the IDDQ of a defective IC will be much higher. During measurement, a test vector is applied to the input of the IC, and then after a specified settling time, the resulting current is measured. After the measurement is completed, the measured current is compared to a preset threshold to determine whether the device passes or fails. This threshold is usually set at the microampere or nanoampere level and is usually determined by IDDQ statistical analysis of multiple intact ICs. As devices become more complex, IDDQ testing cannot always be performed with simple threshold testing. In some cases, statistical analysis of IDDQ data must be performed on the device under test (DUT) to reliably determine pass/fail status. The 2600 Series SourceMeter is ideally suited for both test scenarios.

Test system configuration

Figure 2 is an IDDQ test system based on the 2600 series for CMOS IC.

Figure 2. IDDQ test system configuration

As shown in Figure 2, the HI and LO terminals of the 260X are connected to the VDD and VSS terminals of the CMOS IC. The 260X provides a constant DC voltage to the IC throughout the test. The inputs of the IC are connected to a "digital test system", which ensures that all gates are switched or the required logic states are achieved. It is assumed that this test system also controls mechanical position, DUT detection and disposal of good/bad devices.

The 260X can be controlled like a standard programmable instrument by sending independent commands via the IEEE-488 bus (GPIB) or RS-232. Both communication interfaces on the 260X are standard. However, for maximum throughput, complete test scripts can be downloaded to the instrument's test script processor and all tests performed almost independently of the host PC (system controller). When the 260X is connected to a host controller via GPIB, it can actually control another instrument through its RS-232 port. Therefore, under appropriate circumstances, the 260X can send ASCII command strings to and receive data from digital control systems.

To further increase speed, an external hardware trigger is used to synchronize the IDDQ measurements and the use of test vectors. The 260X is equipped with 14 digital input/output lines that can be used for digital control (pass/fail status in this case) or as input or output trigger lines.

When the vector is sent to the CMOS IC, the digital test system triggers 260X. When the IDDQ value is evaluated, the 260X returns a trigger signal to the digital test system, which generates another test vector. This process is repeated until all test vectors are generated or the IC fails the test. After testing is complete, the 260X writes a predetermined bit pattern to its digital I/O (DIO) port that indicates the pass/fail status of the device to the digital test system.

When the pass/fail status of an IDDQ test is determined solely by comparison of source current to a threshold level, the 260X has at least two methods to accomplish this measurement and check. If the actual value of IDDQ is required, the 260X can measure the current and compare the measured value to a threshold. If the current exceeds the threshold level, the test fails; otherwise, the test passes. The 260X can return any or all measurement values ​​and pass/fail status to the PC host upon request. If the actual value of IDDQ is not required, the 260X can be configured as a digital comparator to achieve higher test throughput. Set the current clamp limit of 260X as the threshold. Apply a test vector and determine the clamp state of 260X. If the current draw attempts to exceed this limit, the 260X will "go into clamp" and clamp the current to this limit. When this happens, the IDDQ test fails. If the current does not exceed this threshold, the device does not enter the clamped state and the test passes. The latter method is usually faster than the previous method because no measurement is required to determine the clamping state of the instrument. As mentioned before, IDDQ testing of complex devices cannot always be achieved with simple threshold testing. In some cases, statistical analysis of IDDQ data must be performed on the device under test (DUT) to reliably determine pass/fail status. After obtaining all test data from 260X, the PC host can perform data analysis. However, the data transmission process is quite slow, which will significantly affect the test throughput.

If there is no need to save readings, then data transfer is too expensive. Used to set up test script processors

The test scripting language includes math libraries and other features that enable extensive analysis within the instrument, eliminating the need to transfer all data. The 260X's deep memory provides further convenience. Two non-volatile buffers per SMU channel can hold up to 100,000 readings. Volatile memory can be used to store more data.