Design scheme of pulse signal measurement based on ADC and FPGA

0Introduction

There are many methods for measuring frequency and pulse width. Usually, the signal parameter measurement based on MCU has a low accuracy because the MCU has a very low operating frequency. The time domain measurement accuracy based on AD10200 and FPGA can often reach 10 ns, and the frequency measurement accuracy is within 100 kHz. The pulse width range of the adapted signal is between 100 ns and 1 ms; the repetition period is between 0.05 and 100 ms; the frequency is between 0.1 Hz and 50 MHz.

AD10200 is a high-speed sampling chip with a built-in transformer, so no transformer is needed outside the sampling circuit, making the circuit design simpler; the minimum sampling rate is 105 MSPS, with 3.3 V or 5 V CMOS compatible output level, dual-channel 12-bit sampling, complement code output, and each channel power consumption is 0.850W. It can usually be used in radar intermediate frequency signal receivers, phase group receivers, communication receivers, GPS anti-interference receivers, etc.

StratixⅡ is Altera's mid-to-high-end mainstream product, which is manufactured using 1.2 V, 90 nm, 9-layer signal routing, and all-copper SRAM technology. StratixⅡ has built-in RAM blocks, DSP blocks, phase-locked loops (PLLs), and external memory interfaces. At the same time, StratixⅡ also adds a new logic structure, the adaptive logic module (ALM), which adds dynamic phase alignment (DPA) circuits and support for new external memory interfaces. The AD chip can work stably at 100 MHz, and the FPGA speed can be as high as several hundred MHz, so the measurement accuracy of the system can be guaranteed.

1 Measurement principle

1.1 Time domain measurement principle

Time domain measurement includes pulse width (PW) measurement and pulse repetition period (Pri) measurement. Time domain measurement can be implemented in FPGA using digital technology. The two inputs of AD are two orthogonal intermediate frequency signals. After the Cordic algorithm, that is, amplitude and phase solution, the amplitude and phase information are obtained, and the amplitude information is used to measure the time domain parameters. The schematic diagram is shown in Figure 1.

When the pulse signal enters the FPGA, it will first perform a threshold judgment to shape the irregular pulse signal into a regular pulse signal. After shaping, the pulse width counter and the repetition cycle counter are started at the rising edge of the pulse signal, and the pulse width counter is latched at the falling edge of the pulse signal and the repetition cycle counter is latched at the rising edge of the next pulse signal; thus, the quantized values ​​N and M of the pulse width and repetition cycle can be obtained, and then the pulse width and repetition cycle can be obtained by calculating the working clock.

1.2 Frequency domain parameter measurement

Frequency domain parameter measurement can be obtained from the phase information carried by the two orthogonal signals. For the input orthogonal sampling I and Q two-way sequence, the angle sequence θ(n)=arctg(I(n/Q(n)) can be obtained by calculating the inverse tangent, but the angle sequence obtained at this time is periodically distributed between (0, 2π), so this angle needs to be defuzzified. The angle sequence can be defuzzified into an increasing straight line, and then defuzzified according to the following formula to obtain a new angle sequence φ(n):

The above formula can be used to accurately calculate the frequency of the pulse signal, thus achieving the purpose of frequency measurement. [page]

2 System Hardware Circuit Design

The hardware circuit principle of the pulse signal measurement system based on AD10200 and FPGA chip EP2S30F48414 is shown in Figure 2. The input signal of this system requires two orthogonal signals. Orthogonal signals are often used in baseband digital signal processing. It can be realized by a variety of methods, such as analog device down-conversion or digital orthogonal down-conversion technology. The characteristics of the two orthogonal signals IQ are similar in amplitude and 90 degrees different in phase. The AD sampling chip is responsible for converting analog signals into digital signals; the power chip is used to power AD, FPGA and MAX232; the crystal oscillator is used to provide the working clock. The reason for choosing a 24.576 MHz crystal oscillator is that when the FPGA communicates with the computer serial port, an analog serial port must be realized, and the selection of 24.576 MHz can just simulate a baud rate of 9600 bit/s, thereby reducing the bit error rate: the external reset can provide an external reset signal for the FPGA. MAX232 is a commonly used level conversion chip that can convert the LVTTL 3.3 V level output by FPGA into the serial port level so that it can be recognized and received by the computer UART port. The system composed of the above chips operates at a frequency of 100 MHz and can achieve fast and high-precision pulse width and frequency measurement. The hardware connection diagram of the sampling chip and FPGA is shown in Figure 3.

3FPGA Software Design

The time domain parameter measurement and frequency domain parameter measurement in this system are performed by FPGA, whose input is two sequences of orthogonal signals, and the output is pulse width (PW), repetition period (Pri) and frequency (f). The digital signal processing flow in FPGA is shown in Figure 4.

In the figure, I(n) and Q(n) are two orthogonal signal sequences; A(n) is the amplitude information sequence; and is the phase information sequence.

After the amplitude and phase calculation of the two orthogonal signal I(n) and Q(n) sequences, the amplitude sequence and phase sequence can be obtained. For the amplitude sequence, after low-pass filtering and normalization, regular pulses can be obtained, and then PW and Pri can be obtained according to the time domain parameter measurement principle; for the phase sequence, the frequency f can be obtained according to the frequency measurement principle; then PW, Pri and f values ​​are stored in the dual-port RAM, and then the stored data is transmitted from the general I/O port of the FPGA through the analog serial port, and input into the computer serial port after MAX232 level conversion, and finally displayed through the host computer to realize human-computer communication.

4 Conclusion

The input signal of this system is required to be an orthogonal signal, which can usually be used for back-end digital signal processing of communication and radar signals. This system uses a phase differential algorithm to calculate the frequency, which is simple to operate and the FPGA speed can be optimized to 200 M. This system uses the high speed of the sampling chip and FPGA to achieve high measurement accuracy and real-time detection. Because it uses an analog serial port for transmission, it has good anti-interference performance.