PCIe 5.0 Specification Latest Updates and Testing Challenges

After the release of PCIe 5.0 Base Specification v1.0 in mid-2019, Synopsys released the world's first IP supporting PCIe 5.0 Base Specification v1.0 and demonstrated the environment for verifying transmitter/receiver Tx/Rx performance in its laboratory. Intel also published an article at the 2019 PCI-SIG Developer Conference showing the analysis and verification scenario of PCIe 5.0 32GT/s SerDes based on 10 nm process. In October, Synopsys and Intel jointly demonstrated a complete system interoperability experiment between Synopsys' DesignWare PCIe 5.0 IP and Intel's next-generation XEON processor.

Despite the pandemic this year, PCI-SIG has still methodically developed PCIe 5.0 CEM specifications and test specifications. PCI-SIG's subordinate working groups, including the CEM working group and the SEG working group, have conducted a lot of online technical discussions and organized virtual workshops and developer conferences. The PCIe 5.0 CEM 0.7/0.9 version specifications have been updated successively, and in October this year, the PCIe 5.0 PHY Test Spec 0.5 version was updated. The release of these versions means that the PCIe 5.0 system specifications and test specifications have entered the final stage of improvement and verification implementation.

Figure 1 PCIE 5.0 specification process

In addition, according to the roadmap released by PCI-SIG last year, based on the plan of upgrading the specification version every two years and doubling the speed, the association will release the PCIe 6.0 specification based on PAM-4 technology in 2021. The association is also currently developing the PCIe 6.0 basic specification. Recently, the association released version 0.7 of the PCIe 6.0 basic specification for review and discussion by association members.

Figure 2 PCIE 6.0 specification is on the verge of being finalized

In order to promote the improvement of PCIe 5.0 test specifications, early verification of chip and system manufacturers, and verification of test equipment manufacturers' test solutions, PCI-SIG plans to hold a preliminary FYI test event for PCIe 5.0 (32GT/s only) at the end of February 2021. The test content includes LEQ, TX/PLL, Link Transaction and Configuration tests, and will also verify the PCIe 5.0 CEM test fixture. The association has now issued an invitation to accept relevant registrations.

The main purpose of this article is to sort out the progress of the key technologies of PCIe 5.0 and the test method ideas. Because the test specifications have not been finalized, some contents are still under discussion in the association and will continue to be optimized and improved in the future. Please pay attention to the subsequent meetings of PCI-SIG and the document specifications it releases. As the only test and measurement solution supplier among the members of the PCI-SIG board of directors, we also welcome experts in the industry to further communicate and cooperate with Keysight.

Updates to PCIe 5.0 CEM Specification and Test Specification

Overall planning and allocation of link loss

The total end-to-end link loss including the CPU and AIC chip package is -36dB @ 16GHz. For the way of transferring by two connectors such as through a riser card, the overall loss margin needs to be considered, and a re-timer chip is usually added to the link. The total loss of the plug-in card AIC is clarified in the latest specifications. Whether it is the transmission path or the reception path, including from the edge of the gold finger through the PCB, vias, isolation capacitors, chip packaging, etc., the total loss cannot exceed -9.5 dB @16GHz. The PCIe 5.0 gold finger slot uses an SMT socket, and the loss cannot exceed -1.5 dB@16GHz. In addition, the typical loss of the CPU package is -8.5dB, and the loss of the AIC chip package is -4.2 dB. Understanding the link loss of PCIe 5.0 will give you a clearer understanding of the topology that needs to be built for transmitter/receiver Tx/Rx testing.

Figure 3 Link margin allocation defined in the PCIE 5.0 CEM specification

Transmitter Tx test index requirements and test methods

1. The PCIe 5.0 CEM defines the transmitter Tx eye diagram indicators of the system motherboard and AIC card as follows:

Figure 4 PCIE5.0 CEM specification transmitter TX end eye diagram indicators

The transmitter Tx test is completed based on the networking environment of the above-mentioned system link allocation, including the test channel and the peer chip packaging model. The specific test networking will be described in detail in the following point 3. In addition, when calculating the signal parameters of the eye diagram, the CDR and receive equalizer (CTLE+DFE) model defined in the PCIe 5.0 basic specification is required, as shown in the figure below.

Figure 5 PCIE 5.0 CDR and equalization model

At present, the official has released the preliminary PCIe 5.0 software tool Sigtest Phoenix 5.0.10 Beta version, which supports most calibration and test scenarios of the basic specification and CEM specification. It is believed that it will be gradually improved in the future.

2. For the test of the system motherboard, PCIe 5.0 32 GT/s no longer uses the Dual Port test method, that is, when testing the transmitter Tx, you only need to connect the differential signal of the test Data Lane to the oscilloscope, and there is no need to capture the differential clock signal at the same time. But one thing that needs to be made clear is that the Dual Port test method is still used at rates of 16 GT/s and below. For the test of 16 GT/s, the coaxial cable connection method is used, and the oscilloscope still needs to maintain a 25 GHz bandwidth when 4 channels are opened at the same time. The figure below shows the test networking method of the PCIe 5.0 32GT/s system motherboard and AIC.

Figure 6 PCIE5.0 CEM transmitter TX test diagram

3. Starting from PCIe 4.0, a variable ISI board fixture has been introduced into the CEM fixture. This fixture is designed with several differential trace pairs with a loss step of close to 0.5 dB. Before the transmitter/receiver Tx/Rx test, it is necessary to use a network analyzer VNA to calibrate and select appropriate trace pairs to build the total link loss target required by the specification. As shown in the figure above, the calibrated ISI trace pairs are cascaded during the Tx test, and the oscilloscope is embedded in the chip package loss at the opposite end.

One change is that for PCIe 5.0 transmitter Tx testing, the association is also considering using S-parameter embedding to replace the variable ISI board, simplifying the above transmitter Tx test network into the following test network diagram, and embedding the link loss S parameter in the oscilloscope in addition to the fixture and test cable:

Figure 7: Network diagram of CEM transmitter TX test simplified by software embedded S parameter method

In PCIe 5.0 PHY Test Spec v0.5, the transmitter Tx test has been required to embed S parameters in this way, but how consistent is the measurement result between this method and the way the hardware ISI fixture is connected? The PCI-SIG Association plans to verify and compare it in the PCIe 5.0 preliminary workshop I mentioned earlier next year. It should be noted that the method of replacing the routing with S parameters is only applicable to the transmitter Tx test, and the receiver Rx test still needs to use the actual variable ISI fixture board.

4. Prior to PCIe 4.0, the specification adopted the Dual Port test method, which evaluated the characteristics of the system transmitter including the reference clock based on the Common Clock architecture of the system motherboard. However, PCIe 5.0 canceled the Dual Port test method and only tested the transmitter Tx signal link characteristics. This may pose certain risks to the interoperability of the motherboard and AIC under the reference clock architecture. Therefore, starting from PCIe 5.0, there are special test requirements for the reference clock of the system motherboard, which will be further explained in the reference clock section.

PCIe 5.0 CEM test fixture update
The figure below is a physical picture of the PCIe 5.0 CEM test fixture. The CEM fixture, like the Base Spec fixture, is suitable for MMPX coaxial connectors and uses low-loss panels. Currently, the CEM fixture is in a small batch state. At the workshop early next year, correlation verification will be carried out with instrument manufacturers.

Figure 8 PCIE 5.0 fixture

The fixture kit includes CBB, CLB and variable ISI boards, and several MMPX short lines. A VNA with a frequency range of at least 20 GHz is required to measure the losses of cables, fixture PCBs, connectors, CEM slots, etc. at the Nyquist frequency point of 16 GHz for PCIe 5.0 32GT/s. The ISI trace pairs required for Tx and Rx test target losses are selected. The overall measurement and calibration method is similar to PCIe 4.0. As shown below, the actual test image of measuring the complete channel networking loss using Keysight PNA-X series VNA and the calibration fixture flow chart are shown.

Figure 9 PCIE4.0/5.0 complete test network link loss verification schematic and flow chart

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Several issues on PCIe 5.0 CEM Tx testing

CEM Tx test bandwidth and sampling rate requirements

In the PCIe 5.0 PHY Test Spec, for the AIC or system motherboard Tx signal quality consistency test, the oscilloscope bandwidth is required to be set to 33 GHz and the sampling rate is at least 128 GSa/s. If the oscilloscope hardware sampling rate does not meet this requirement, Sin(x)/x interpolation is allowed, but at most one interpolation point is allowed, which is at most twice the original sampling rate, to ensure that each UI has at least 4 sampling points.