Memory chips, DDR5 technology and complete testing solutions

A brief history of memory

Memory chips are an important part of digital chips. They can store programs and various data, and can automatically access programs or data at high speed during computer operation. The following are the basic classifications of memory chips:

Figure: Basic Classification of Memory

The memory is mainly divided into two categories: read-only memory ROM and random access memory RAM, as briefly described below:

What is Read Only Memory ROM

The data stored in the read-only memory ROM is generally written in advance before being installed in the whole machine. It can only be read during the operation of the whole machine. The data stored in the ROM is stable and will not change after power failure.

What is RAM (random access memory)?

Random Access Memory (RAM) is an internal memory that directly exchanges data with the CPU. It can be read and written at any time at a fast speed. It is usually used as a temporary data storage medium for the operating system or other running programs. RAM cannot retain data when the power is turned off.

DDR SDRAM, which is also our protagonist today, is developed on the basis of SDRAM. This improved DRAM is basically the same as SDRAM, except that it can read and write data twice in one clock, which doubles the data transmission speed. It is also the most used memory in computers and has cost advantages. DDR has evolved to DDR5. Compared with DDR4, DDR5 brings a new architecture in a powerful package. Below we will focus on DDR5 technology and test solutions.

Introduction to DDR5

The DDR bus has evolved and has now developed to DDR5. The following figure shows the evolution of the DDR bus:

Figure: DDR technology evolution

Whether in the fields of mobile computing, PC, server or graphics computing, the bus has evolved from the early low-speed simple timing characteristics to the application of technologies such as DFE in DDR5. The memory bus is gradually introducing SerDes technology and gradually approaching the channel transmission limit. With the official release of the DDR5 specification, entering 2021, DDR5 has begun to be adopted by server CPU and memory manufacturers, with higher data rates, lower energy consumption and higher density.

DDR5 has the following features:

· Higher data rates·
DDR5 has a maximum data rate of 6400MT/s (million times per second), while DDR4 is 3200MT/s, and the effective bandwidth of DDR5 is about twice that of DDR4.
· Lower energy consumption·
DDR5 operates at 1.1V, lower than DDR4's 1.2V, which can reduce power consumption per unit bandwidth by more than 20%
· Higher density·
DDR5 increases the burst length to BL16, about twice that of DDR4, improving command/address and data bus efficiency. The same read or write transaction now provides twice the data on the data bus while limiting the risk of input/output/array timing constraints within the same memory bank.
In addition, DDR5 doubles the number of storage groups, which is a key factor in improving overall system efficiency by opening more pages at any given time. All of these factors mean faster and more efficient memory to meet the needs of next-generation computing.

Meeting the Challenges of DDR5 Testing

As mentioned above, DDR5 has many advantages, but it also greatly increases the difficulty and complexity of testing. As a leader in the testing industry, Keysight has been actively promoting the development of JEDEC DDR5 specification test solutions, and has worked with leading partners in the industry to promote the evolution and implementation of the specification, from DDR bus simulation, test fixture definition and development, Rx testing and Tx testing stringent jitter quality requirements, to the development of protocol testing methods. Keysight is also the only provider of complete DDR5 Tx/Rx physical layer to protocol testing solutions, as shown below:

Figure: Keysight Technologies DDR5 solution

Keysight Technologies provides complete solutions for different product forms in the DDR ecosystem, as shown in the figure below, including transmitter testing, receiver testing, protocol testing, etc. We will introduce them separately below.

Figure: Keysight Technologies' complete DDR product form factor solution

DDR5 Transmitter Test

With the increase in signal rate, SerDes technology has begun to be used in DDR5. For example, the DFE equalizer will be used to improve the receiving bit error rate. In addition, the DDR bus has introduced a training mechanism during its development. It no longer simply requires the absolute setup and hold time between signals. The concept of eye diagram was used in the DDR4 era, and the concept of jitter components was introduced in the DDR5 era. Rj, Dj, etc. are distinguished from the cause, providing a more specific basis for chip or system design. In the parameter analysis of jitter, some new jitter definition parameters have also been added, with strict measurement indicators.

Keysight Technologies provides a complete solution for these requirements. Based on Keysight Technologies' 10-bit ADC  UXR oscilloscope ,  D9050DDRC transmitter consistency software , high-impedance RC probe MX0023A , and Interposer, accurate characterization of DDR signals can be achieved.

Figure: DDR5 transmitter test diagram based on UXR oscilloscope