Oscilloscope cross real-time sampling evaluates the relationship between oscilloscope sampling rate and sampling fidelity

How can oscilloscope vendors create oscilloscopes with higher sampling rates when ADC technology has reached its limits in terms of maximum sampling rate? The pursuit of higher sampling rates may simply be a desire to satisfy oscilloscope users’ perception that “higher is better” or that users may actually need higher sampling rates to achieve higher bandwidth real-time oscilloscope measurements. However, making an oscilloscope with a higher sampling rate is not as simple as selecting an off-the-shelf analog-to-digital converter with a higher sampling rate.

A common technique used by all major oscilloscope vendors is to interleave multiple real-time ADCs. However, this interleaved sampling technique should not be confused with the repetitive acquisition technique, which we call “equivalent-time” sampling.

Figure 1 shows a real-time interleaved ADC system block diagram consisting of two ADCs using phase-delayed sampling techniques. In this example, ADC 2 always samples ½ clock cycle after ADC 1 samples. After each real-time acquisition cycle is completed, the oscilloscope's CPU or waveform processing ASIC retrieves the data stored in each ADC acquisition memory and then interleaves the samples to obtain a real-time digitized waveform with double the sample density (twice the sampling rate).

Oscilloscopes with real-time interleaved sampling features must comply with two requirements. First, to achieve accurate interleaving without distortion, the vertical gain, offset, and frequency response of each ADC must be strictly matched. Second, the phase-delayed clock must be calibrated with high precision to meet the requirements of Nyquist Rule II, which is equally spaced sampling. In other words, the sampling clock of ADC 2 must be delayed exactly 180 degrees after the sample ADC 1. Both conditions are very important for accurate interleaving. However, in order to have a more intuitive understanding of the errors caused by poor interleaving, the following article will focus on the errors caused by poor phase-delay timing alone.

Figure 1: Real-time sampling system consisting of two interleaved ADCs

The timing diagram shown in Figure 2 illustrates that interleaved sampling can have timing errors if the two interleaved ADC phase-delayed clock systems are not exactly ½ sample period delayed from each other. The diagram shows the points digitized in real time (red dots) relative to where the input signal actually transitions. However, due to the imperfect phase-delay timing alignment (purple waveform), these digitized points are not sampled equally spaced, thus violating Nyquist's second rule.

When the oscilloscope’s waveform processing engine retrieves the data stored in each ADC acquisition memory, it first assumes that the samples in each memory device are equally spaced. When you try to reconstruct the shape of the original input signal, the signal represented by the oscilloscope’s Sin(x)/x reconstruction filter will be severely distorted (as shown in Figure 3).

Real-time acquisition distortion (sometimes called “sampling noise”) can be misinterpreted as random noise when you view repetitive acquisitions because the phase relationship between the input signal and the oscilloscope’s sample clock is random. However, this phase relationship is not completely random, but rather has some determinism and is directly related to the oscilloscope’s sample clock.

Figure 2: Timing diagram for non-equally spaced sampling

Figure 3: This timing diagram shows a waveform distorted by poor phase delay timing, reconstructed using a Sin(x)/x filter.