Application of NAND FLASH in storage test system

0 Introduction

With the rapid development of computer technology, the storage system capacity has expanded rapidly from a few KB storage space in the past to T8 today, and even to PB storage space in the near future. The new fields such as SCSI, FC, SAN, iSCSI, IPStorage and data lifecycle management that have emerged have given computer technology and network technology a vigorous vitality. The improvement of storage performance is usually achieved by adding more physical disk drives to the infrastructure or using disk drives with faster rotation speeds.

Airborne storage devices are required to have high reliability and high resistance to impact, vibration, moisture, high pressure and high temperature. However, disk drives have mechanical rotation when accessing data, and their impact and vibration resistance are not strong, so they are not suitable for use in harsh environments such as aerospace. The emergence of solid-state storage (SSD) based on semiconductor memory chip flash memory has solved the above problems well. As a storage medium, SSD has no mechanical rotating parts, high storage density, high reliability, small size, light weight, and is resistant to vibration, shock, and a wide temperature range. It has strong environmental adaptability and can meet data storage requirements under harsh conditions. Therefore, high-performance and large-capacity solid-state storage has become the only data storage method in major military projects.

1 NAND FLASH Memory Control Requirements

1.1 Introduction to NAND FLASI-1 memory structure and functions

We use Samsung's K9K8G08UOM FLASH chip as the medium of the storage system. The storage capacity of this NAND F1ash is 8448Mbit, of which the main data area is 8192Mbit, the auxiliary data area is 256Mbit, the working voltage is 2.7V~3.6V, and the width of the I/O port is 8 bits. NAND FLASH is different from NOR FLASH. NOR FLASH does not allow bad blocks to exist in the chip when it leaves the factory, while NAND FLASH allows bad blocks in the finished product, which is a phenomenon unique to NAND technology.

The 8448M bit memory in the chip is organized according to the concept of blocks and pages. A FLASH memory contains 8192 blocks, each block contains 64 pages, and each page has 2112 bytes. The chip has a data register with a capacity of 2112 bytes, called a page register, which is used as a buffer when accessing data. When reading and writing a page in the chip, the data is first transferred to this data register, and the data is exchanged with the outside of the chip through the data buffer to complete the read and write functions. The 2112 bytes in the page are divided into a main data area of ​​2048 bytes and an auxiliary data area of ​​164 bytes. The main data area stores user data, and the auxiliary data area is used to store ECC (Error correction Code), bad block information and file system related codes. Its organizational relationship is shown in Figure 1:

The address of K9K8GOSUOM is sent to the chip by multiplexing 8 I/O ports. This design significantly reduces the number of pins of the chip and brings convenience to system upgrades. When CE and WP are low, setting WE low can write the command, address and data of K9K8G08UOM through the I/O port. Data is written to the chip on the rising edge of WE. Command latch enable (CLE) and address enable latch (ALE) are used to distinguish whether the data of the I/O port is a command or an address. K9K8G08UOM has a 1G byte address space and requires a 30-bit address, so the byte address needs five cycles to be sent in sequence: row low address, row high address, column low address, column middle address, column high address. Page read operations and programming operations require the same five address cycles following the corresponding command input. However, in the block erase operation, only three address cycles are required. Different operations are distinguished by writing different commands to the command register. [page]

1.2 K9K8G08UOM controller technology

In this system, FPGA is used as the controller of K9K8G08UOM memory, which can independently complete various operations of K9K8G08UOM with very few software operations, thereby reducing the system's additional expenditure on FLASH memory and improving the reading and writing speed. The control logic timing of FPGA is developed through the hardware language VHDL. VHDL language has the advantages of fast, independent and readable to complete the timing control of basic FLASH operations. The following is a part of the read operation program developed in the form of a state machine in VHDL language.

The basic operations of K9K8G08UOM memory are divided into three types: read operation, page programming operation, and erase operation. The flow chart is shown in Figure 2.

When performing a read operation, first set the chip select signal /CS of K9K8G08UJOM low through the FPGA port, then set the CLE command pin high, and send the read1 (0x00) command, which is sent at the rising edge of WE. After the command is sent, set CLE low. Before sending the address, set ALE high, write 5 address cycles in sequence at each WE rising edge, and then set ALE low to complete the address selection. Then send read2 (0x30h) to start reading the data of the address unit.
The data page programming operation is similar to the read operation process. The operation is performed in pages. When the R/Bur signal is low, it means that FALSH is being written, and when it is high, it means that the page programming operation is completed.

The erase operation is performed in blocks, that is, 64 pages in a block are erased at a time, and only three address cycles are required when sending the address.

Figure 3 shows the data read by the host computer software after the data is stored in the K9K8G08UOM memory. It has been verified that the read data is consistent with the data written into the K9K8G08UOM memory.

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2 Hardware of NAND FLASkI Memory

In this design, the data input and output ports and control ports of FLASH are connected to the ports of FPGA through conditioning circuits. Figure 4 shows the hardware connection circuit.

As shown in Figure 4, the data input and output ports I/00~7 and the control port /CE of FLASH are connected to FPGA through chip SN54LV245; the control ports CLE, ALE, /WE, and /RE of FLASH are connected to ITGA through chip SN54LV245 and chip 74HCl4. Among them, F-CLE, F-ALE, F-WE, F-RE, F-CE, and F-R/Bur are the I/O ports of FPGA and the input and output ports of FPGA logic. CLE and ALE signals are FLASH memory command and address latch enable signals, /WE is a signal to ensure that the command, address, and data can be written into FLASH in time and correctly, and /RE signal controls the reading of data. The accuracy of these signals is related to the realization of FLASH storage and reading functions. Therefore, the quality of these signals is directly related to the normal operation of FLASH. After practical circuit debugging, these signals are interfered by other factors during the transmission process, and the signals are obviously distorted. After adding 74HCl4 (not gate) to the circuit, the signals will become smooth and accurate.

The chip SN54LV245 is an octal three-state bus transceiver. When DIR=1, the bus transmission direction is from A→B; when DIR=0, the bus transmission direction is from B→A. /OE is the chip select signal. /0E, the DIR signal is controlled by the programming logic inside the FPGA.

In the FL,ASH interface, in order to ensure that the initial state of the /WE, /RE, /CE, and R/B control signals is invalid, the port value is pulled high by the hardware circuit. The write protection function is not used in this design, so the /WP port is also connected to a pull-up resistor.

3 Conclusion

Solid-state memory based on flash memory technology has high storage density, low power consumption, high reliability, small size and light weight, and its cost is also decreasing. It has good application prospects in aviation applications. When designing a storage test system, the large-capacity NAIXD FLASH memory is used to greatly improve the storage and reading speed, and the circuit structure is simple and easy to modify.