Yu Xiekang: Collaborative innovation promotes the development of China's integrated circuit packaging and testing industry

On July 25, 2017, Yu Xiekang, Secretary General of the IC Branch of China Semiconductor Industry Association and Secretary General of the National IC Packaging and Testing Industry Chain Technology Innovation Strategic Alliance, delivered a keynote speech entitled "Collaborative Innovation to Promote the Development of China's IC Packaging and Testing Industry" at the 11th China Semiconductor Industry Association Semiconductor Discrete Devices Annual Conference and 2017 China Semiconductor Devices Innovation Products and Applications and Industry Development Forum. Let's learn about the relevant content with the test and measurement editor.

Secretary-General Yu Xiekang's report is divided into three parts. The first part reviews the development history of China's integrated circuit packaging and testing industry; the second part talks about the opportunities and challenges of China's integrated circuit packaging and testing industry; and the third part proposes the future development path of China's integrated circuit packaging and testing industry - collaborative innovation.

The following is compiled based on the speech of Secretary-General Yu Xiekang.

1. Development History of China's Integrated Circuit Packaging and Testing Industry

China's integrated circuit packaging and testing industry occupies an important position in the industrial chain. Among the three major industries of design, chip manufacturing and packaging and testing, the scale of the packaging and testing industry has been higher than the international general level in recent years, reaching 36.1% in 2016.

China's integrated circuit packaging and testing industry started late and has generally gone through the following four stages of development:

The first stage is the initial stage, which was roughly in the 1980s. During this period, through-hole packaging was the main technology, and the main representative technology was DIP (dual in-line package). Secretary-General Yu introduced that China's integrated circuit packaging was started by Huajing Electronics in 1978.

The second stage is the key development stage, which was roughly in the 1990s and entered the era of surface mount. The main representative technologies are SOP (small outline package) and QFP (quad flat package). The main feature is that the pins are led out from two or four sides, and the installation method is changed from plug-in to surface mount, which can greatly increase the number of pins and assembly density compared to the plug-in method; the overall scale of the industry during this period was relatively small.

The third stage is a stage of comprehensive and rapid development, which was roughly the beginning of the 21st century. Before 2006, the domestic packaging and testing industry had begun to study surface mounting technology that replaced pins with solder balls and distributed in the form of area arrays. The main representative technologies were ball grid array packaging BGA and multi-chip packaging MCP. From 2006 to 2010, a number of technologies such as QFN, BGA, and CSP were put into mass production. Compared with the previous period, packaging technology had a major breakthrough and the scale of the industry has expanded significantly. In 2009, Changdian Technology ranked among the top ten global packaging and testing industries for the first time.

The fourth stage is the leapfrog development stage from 2011 to the present. The technical characteristics of this period are high density and miniaturization. The main representative technologies are wafer-level chip size packaging (WLCSP) and flip-chip ball bond array packaging (FCBGA). In particular, as the chip feature size has approached the physical limit and the original method of increasing packaging density by reducing the feature size has encountered a bottleneck, packaging technologies represented by 3D packaging and 2.5D through silicon vias have emerged and become a technical highlight of the packaging and testing industry in recent years. The overall technical level has further narrowed the gap with the international level, and some packaging technologies have reached the international leading level.

According to research data from France's YOLE, Changdian Technology ranks third in the world in advanced packaging processes with a share of 7.8%, second only to Intel and Siliconware Precision Industries.

According to the sales scale data of China's integrated circuit packaging and testing industry from 2010 to 2016 provided by the Packaging and Testing Alliance, it can be seen that China's integrated circuit packaging and testing industry has developed rapidly. In the six years since 2011, sales revenue has increased by 1.5 times compared with 2010, with a CAGR of 16.39%.

Secretary-General Yu Xiekang said that in comparison of the advanced packaging technology levels at home and abroad, the three major advanced packaging technologies for integrated circuits in China: SIP system-level packaging (Jiangdian, Huatian), WLP wafer-level packaging (Jiangdian, Jingfang), and FC flip-chip (Jiangdian, Tongfu) packaging technologies are all available and have made breakthroughs, and the technical capabilities are basically close to the international advanced level. Advanced packaging accounts for about 20%, but the domestic packaging industry as a whole is still dominated by traditional low-end packaging, such as SOP (SSOP, TSOP), QFP (LQFP, TQFP), QFN/DFN, etc. It is expected that the demand for high-end advanced packaging technology will increase in the future.

From the "China Integrated Circuit Packaging and Testing Industry Technology Development Roadmap" published by the Packaging and Testing Alliance, it can be seen that my country has a very complete range of packaging types.

From the perspective of industry scale, the development speed of the domestic packaging and testing industry has been higher than the overall development speed of the international packaging and testing industry for many years, but there is still a big gap between the overall packaging technology level and the international level.

In terms of wafer-level packaging (WLP) technology, China mainly adopts Fan-in technology, mainly mass-producing WLCSP products; small-scale mass production of Fan-out has just begun, and overseas technology has developed in a diversified manner. Fan-in, Fan-out, embedded WLP and wafer-level 3D stacking packaging technologies have matured.

In terms of flip chip (FC) technology, all domestic enterprises use traditional mass reflow technology. Overseas enterprises have mass-produced TCB-bonded FC packaging technology. The size of chips assembled by domestic enterprises has not exceeded 20x20mm. Foreign enterprises have advantages in mounting accuracy and stability. For example, Universal Instruments' equipment solutions for flip chip assembly take into account the characteristics of high speed and high precision.

PoP packaging technology. At present, China has not yet achieved mass production of advanced PoP packaging; some foreign companies are mass producing Bare Die PoP packaging, and overseas companies are already using advanced Substrate Interposer technology.

TSV (2.5D/3D) technology. The application of TSV in China is mainly in the packaging of CMOS Image Sensor, which is a relatively low-end and primary TSV technology. For the application of high-end TSV, domestic enterprises are in the R&D stage. Internationally, TSMC, Samsung, ASE and other international companies have the ability to achieve a 10:1 aspect ratio with a 10-micron aperture.

2. Opportunities and Challenges of China's IC Packaging and Testing Industry

After years of development, my country's integrated circuit packaging and testing industry has ushered in good development opportunities.

First, in terms of industrial foundation, in the early 21st century, based on comprehensive factors such as labor costs and domestic industrial policies, international packaging and testing foundries successively invested in and established packaging and testing bases in Shanghai, Shenzhen, Wuxi, Suzhou, Chengdu and other places in China. In recent years, domestic enterprises and international manufacturers have merged and reorganized, which has improved the competitiveness and technical level of China's packaging and testing industry.

Secondly, in terms of policy opportunities, the release of the "National Integrated Circuit Industry Development Promotion Outline" has attracted good policy support, and central and local integrated circuit industry funds have been established one after another, and the domestic integrated circuit industry has ushered in a new development climax. The "Promotion Outline" clearly states that "the development level of the advanced packaging and testing industry will be improved. Under the background of the overall rapid development of the industry, the rapid development of the domestic design industry and manufacturing industry and the trend of packaging localization have provided more development space for domestic packaging and testing companies."

Finally, as for the technology development trend, Moore's Law has encountered a bottleneck so far, and the feature size of chips has approached the physical limit. Advanced packaging technology has become the inevitable choice to continue Moore's Law. With the rise of "packaging and testing middle road" and the rapid development of advanced packaging, the packaging and testing industry has changed its previous subordinate position in the three industries of integrated circuits, and its importance has become apparent.

Rethinking the Post-Moore Era

At present, typical SiP technology can include a variety of advanced packaging technologies that have been developed and continuously developed in the field of packaging technology, such as WLP, Flip Chip, 3D packaging, TSV technology, IPD, Embedded PCB/Substrate, etc. From the perspective of the development direction of the post-Moore era, the development trend of packaging and testing technology will surely bring unprecedented development opportunities for industrial development.

The first is to continue Moore's Law: continue to proportionally reduce the process feature size of CMOS devices, increase integration, and improve circuit performance through the use of new materials and innovation of device structure. The development direction of this law is IC design and manufacturing, mainly SoC technology.

The second is to expand Moore's Law: driven by market and application demands, in order to meet the diversification of functions, the functional diversification represented by system-level packaging (SiP), especially fan-out packaging and panel-level packaging, is listed as a new direction for the development of semiconductor technology. This technology focuses on increasing the multiple functions of system integration.

Due to the mid-process technology brought about by the advanced packaging process, the packaging and testing industry and the wafer manufacturing industry have become closely linked. While attracting good development opportunities, they are also facing new challenges.

The rise of the packaging mid-stream will inevitably squeeze the share of the wafer manufacturing industry. There are signs that some wafer fabs have increased their layout of the packaging mid-stream process. Since wafer fabs have leading advantages in technology and capital, they will create greater competitive pressure on packaging and testing plants.

Compared with the wafer manufacturing industry, traditional packaging and testing plants are asset-light. After the introduction of mid-stream processes, the proportion of equipment assets has greatly increased compared with traditional packaging. The advanced technology research and development and expansion of the packaging and testing industry will face greater financial pressure. It is difficult for domestic packaging and testing companies to have stable and continuous investment relying solely on their own financial resources. (Subsequent introduction of large funds or industry collaboration, Changdian + SMIC)

The integrated circuit industry in the post-Moore era places more emphasis on close cooperation within the industrial chain. The packaging and testing industry will play an important role. How to effectively concentrate the advantageous resources of the industrial chain to develop packaging and testing technology is also a major challenge during this period.

The development of the integrated circuit industry is inseparable from professional talents. The packaging and testing industry can solve the talent problem through mergers, reorganizations and introductions in the near future. How to cultivate high-end talents needed by the industry to meet the needs of the continuous development of packaging and testing technology is a major challenge facing the future.

How to solve the gap between China and foreign countries in terms of talent, technology and management? Of course, in the near future, we can solve the talent and technology problems through mergers and acquisitions and introduction, but the integration work after mergers and acquisitions is very difficult. Therefore, cultivating high-end talents needed by the industry to meet the needs of the continuous development of packaging and testing technology is a major challenge in the future.

Secretary-General Yu Xiekang particularly emphasized that there is no shortage of production and management personnel in my country's packaging industry, and the front-line engineers should basically be able to meet the needs, but there is an extreme shortage of high-end R&D personnel and system design talents.

Challenges facing packaging and testing industry technology

The driving forces for the development of advanced packaging technology are mainly: first, cost drive to reduce the cost of the entire system; second, gradually achieve product differentiation through advanced packaging technology; third, functional drive to increase device placement density (improve signal performance); fourth, higher density interconnection substrate process technology; fifth, high performance, high density and miniaturization drive.

To meet these requirements, the challenges faced by the technological development of the packaging and testing industry mainly include four common problems and four types of key technologies; the core is to meet the requirements of high cost performance, short and light.

Four common issues: system-level packaging design and tools, high-density functionalized substrates and materials, system-level packaging reliability, and system-level packaging testing methods.

Four key technologies: key processes for high-density packaging, key technologies for three-dimensional packaging, key technologies for multifunctional chip stacking integration, and key technologies for system-level packaging.

III. Future Development Path of China's Integrated Circuit Packaging and Testing Industry - Collaborative Innovation

Secretary-General Yu Xiekang believes that the demand for packaging technology is getting higher and higher, and the cooperation between packaging and design, manufacturing, equipment, materials, system manufacturers, research institutes, and universities is becoming closer and closer. After market testing, five major collaborative innovation models have been spontaneously formed.

1. Huajin Model. Its characteristics: Common technology research and development

As an industry common technology research and development platform, the establishment of Huajin Semiconductor marks the establishment of a national packaging technology innovation center, which has a great role and significance in the country's future innovation in integrated circuit packaging technology. It is also a useful exploration of the corporate innovation collaboration model in the post-Moore era.

From the development history of the entire integrated circuit industry, we can see that there are enterprises independently expanding their scale, mergers and reorganizations within the industry, market demand has spawned new technology breakthroughs that drive industrial development, such as smart phones, the Internet of Things, etc., and policy guidance promotes industrial development. There are also successful typical cases of international industrial development models, such as TSMC's vertical division of labor model (Foundry), the fabless IC design company model without a production line (Fabless), Samsung's IDM+ complete machine manufacturing model, etc. The domestic packaging and testing industry has also experienced a transition from being a part of the IDM model to a professional outsourced packaging and testing foundry (OSAT) model.

As a common technology research and development platform for the industry, Huajin Semiconductor was jointly established by several leading domestic packaging and testing companies with competing relationships and the Institute of Microelectronics of the Chinese Academy of Sciences. It also marks the establishment of a national packaging technology innovation center. It plays a significant role and significance in the country's future innovation in integrated circuit packaging technology, and is also a beneficial exploration of the innovation and collaboration model of enterprises in the post-Moore era. In recent years, Huajin Semiconductor R&D Center has achieved certain results in IC advanced packaging R&D and innovation, especially in 3D (TSV) system-level packaging (SiP). For example: 2.5D/3D multi-chip high-density interconnection integration based on TSV; Bumping, WLCSP, and Fan out technologies based on wafer-level packaging; and FC, multi-chip module (Multi-Chip Module/MCM) 2D/3D SiP packaging system integration technology, and many technologies are in a leading position in China. Practice has shown that the Huajin model has effectively resolved the contradiction between competition and cooperation among enterprises, fully utilized the advantageous resources among enterprises, and solved issues such as the ownership of intellectual property rights during the R&D process. The R&D platform has played a very good role in promoting the overall technological level of the industry.

2. SMIC Longye Model. Its characteristic is the wafer + packaging collaborative model

With the birth of "Zhongdao", the cooperation between packaging and testing companies and chip manufacturing companies has become a new collaborative model. Currently, TSMC has established its own Zhongdao packaging line.

In February 2014, JCET and SMIC formally signed a contract to establish a joint venture with 12-inch bump processing and supporting testing capabilities. The establishment of bump processing and nearby supporting production lines with advanced packaging processes such as flip-chip, combined with SMIC's front-end 28-nanometer advanced process, formed a 12-inch semiconductor manufacturing industry chain. SMIC JCET Semiconductor adopts a pure foundry model, focusing on the development and manufacturing of advanced semiconductor mid-stage processes, and focusing on the development of advanced 12-inch bump processing (Bumping) and supporting wafer chip testing.

At present, Huatian Technology has signed strategic cooperation agreements with Wuhan Xinxin, Tongfu Microelectronics with Huali Microelectronics. So far, the three leading domestic packaging and testing companies have successively carried out collaborative innovation with wafer foundries.

3. Collaborative design mode. Its characteristics: application design and packaging collaboration

This is an innovative design + packaging model based on product development. In the past, the design of chips, packages and circuit boards was mainly implemented in sequence. The signal integrity problems faced by circuit board designers were generally solved through unoptimized designs. Later, such problems began to adopt a system approach. Due to inherent time constraints and short design cycles, it is extremely challenging to establish system synergy between chips, packages and circuit boards. Today, as chip functions, power management, etc. become more and more complex, the structure of the package is also becoming more and more complex. The traditional design of "IC-package-PCB" is no longer applicable to today's products. Comprehensive collaborative design between IC-package-substrate has become inevitable.

4. Consortium model. Its characteristics: industrial chain collaboration

This is based on the collaborative innovation model of the packaging and testing industry chain, which can be applied to the research and development of new packaging and testing technologies, new equipment, and new materials. The members of Huajin Semiconductor's "Technology Consortium" are mainly composed of well-known domestic and foreign semiconductor companies, end users, packaging and testing companies, materials, equipment suppliers and other complete integrated circuit industry chains. They use the resources and technical advantages of leading enterprises in each industry chain to jointly develop advanced packaging technology. During the research and development process, the research and development samples are circulated among the member units, and the member units are responsible for the design, manufacturing, packaging and testing, verification and other tasks. The "consortium" shares technical achievements and intellectual property rights. Once the research and development technology is converted into a complete set of technology, the "consortium" members will automatically become a part of the advanced packaging industry chain. Through this model, the superior technologies, talents and resources of the industry chain can be effectively coordinated to solve the difficulties of lack of funds, talents, technology and equipment in the early stage of research and development of key technologies, large equipment and core materials. Practice has shown that many technology and equipment consortium models have achieved fruitful results, including the successful organization of internationally renowned packaging experts to come to China for exchanges; the completion of multiple sets of domestic equipment evaluation; the organization of equipment suppliers and users exchange meetings, feedback on the use of domestic equipment, and promote the implementation of improvement plans. Huajin Semiconductor has also become a verification platform for domestic high-end packaging and testing equipment and materials. This innovative model has made a positive contribution to exploring the development of my country's integrated circuit packaging industry chain. The earliest representative of the consortium is the "TVS Consortium".

5. Industry-university-research-application collaborative model. Its characteristics: public services and basic research

The public service platform and talent training base are mainly established through the collaboration of industrial chain + universities + research institutes. The establishment of the industry-university-research-application collaborative innovation platform fully utilizes the innovation platforms and resource advantages of key backbone enterprises relying on enterprise technology centers, academician workstations, engineering research centers, etc., and jointly establishes public service platforms with universities and research institutes to build innovation platforms that serve enterprises, integrate industrial technology innovation resources, carry out collaborative innovation, break through key major technologies that restrict the development of my country's industries, and cultivate professional talents according to the needs of industrial development.

The above is an introduction to Yu Xiekang in Test and Measurement: Collaborative innovation promotes the development of China's integrated circuit packaging and testing industry. If you want to know more related information, please pay more attention to eeworld. eeworld Electronic Engineering will provide you with more complete, detailed and updated information.