A detailed analysis of common digital I/O and logic analyzer terms

　　This article introduces common terms and definitions for digital I/O and logic analyzers.

　　1. Jitter

　　Jitter is the deviation from the ideal timing of events and is usually measured based on the zero crossings of a reference signal. Jitter often comes from crosstalk, synchronous switching outputs, and other interfering signals that occur at regular intervals. Because jitter varies over time, jitter can be measured and quantified either as a visual estimate in the second range or based on statistical measurements, such as standard deviation over time.

　　Figure 1. Example of digital signal jitter

　　2. Offset

　　For timing (dynamic) generation, channel-to-channel skew is defined as the time difference between the corresponding edges of two data channels. For example, if two data channels are set to transition from low to high at a specific sample time, the time difference between the rising edges of the two channels is the channel-to-channel skew between the two channels.

　　For dynamic acquisition, channel-to-channel skew is defined as the difference between the sampling times of each data channel. Each time a sampling point is acquired, the sampling time of each data channel is different, but the time difference between them is very small and usually falls within a specific time window. This time window is called channel-to-channel skew.

　　The following figure shows the channel-to-channel skew for a set of signals.

　　Figure 2. Example of digital signal offset

　　The specified inter-channel skew generally refers to the skew between all data channels on a device.

　　3. Rise time and fall time

　　The rise time (trise) refers to the time it takes for a signal to rise from 20% of the high level to 80% between high and low levels. The fall time (tfall) refers to the time it takes for a signal to fall from 80% of the high level to 20% between high and low levels.

　　Figure 3. Digital signal rise time and fall time diagram

　　4. Overshoot and undershoot

　　Preshoot and overshoot mainly refer to the peak distortion of the instantaneous level of the pulse before (preshoot) or after (overshoot) the rising or falling edge of the pulse. Figure 4 shows an example of signal preshoot and overshoot.

　　Note: Overshoot, preshoot and undershoot are abnormal phenomena.

　　Figure 4. Digital signal overshoot, preshoot, and undershoot diagram

　　5. Stabilization time

　　Settling time (tS) is the time required for an amplifier, relay, or other circuit to reach stable operation. For signal acquisition, the settling time of a full-scale step is the time it takes for the signal to reach a certain accuracy and remain within this accuracy range.

　　Figure 5. Settling time diagram of a digital signal

　　6. Duty Cycle

　　For clock signals, the duty cycle is the ratio of the time that a waveform is at a logic high level to the period of the waveform. The following figure shows the difference between two waveforms with different duty cycles. Note that the waveform with a 30% duty cycle spends less time at a logic high level than the waveform with a 50% duty cycle.

　　Figure 6. Digital signal duty cycle diagram.

　　7. Hysteresis

　　Hysteresis is the difference in voltage levels when a signal is detected to transition from logic high to logic low and from logic low to logic high. See Figure 7 for an illustration of hysteresis.

　　Figure 7. Hysteresis plot of a digital signal

　　All digital logic devices have some degree of hysteresis on their digital inputs. The magnitude of hysteresis for a particular device can be calculated using the following formula:

　　Hysteresis ≈ VIH - VIL

　　On the rising edge of the digital signal at the input, the device detects the signal transitioning from logic low to logic high at VIH. Conversely, when the voltage at the device input is below VIL, the device detects the signal transitioning from logic high to logic low.

　　Hysteresis is a very useful property of digital devices because it provides a degree of rejection of high frequency noise in digital systems. This noise is usually caused by reflections from the high edge rates of logic level transitions and can cause digital devices to make erroneous level transition detections if only one voltage threshold is used to determine the change in logic state. This phenomenon can be clearly seen in Figure 8.

　　Figure 8. Potential effects of noise on hysteresis

　　In this figure, the first sample point is a logic low level. The second sample point is also a logic low level because the signal level has not crossed the high level threshold. The third and fourth sample points are logic high levels, and the fifth sample point is a logic low level.

　　For devices with fixed voltage thresholds, the noise immunity (NIM) and hysteresis of the system are determined by the components of the system. For example, some NI digital I/O devices allow you to control the NIM and hysteresis of the system. The system NIM and hysteresis can provide a certain level of noise immunity to the system, but for a particular logic device, there is usually a trade-off between the two—more hysteresis means less NIM, and vice versa. To properly set voltage thresholds, you must carefully examine the signal quality of your system to determine whether you need more noise immunity (higher NIM) at high and low levels or more noise immunity (higher hysteresis) at logic level transitions.