Analysis of Glitch Signals in Logic Analyzer Hardware Circuits

　　Glitches are often the "culprit" of hardware failures, but because they last very short, have small amplitudes, and "come and go without a trace", they are difficult to capture with an oscilloscope, which gives engineers a headache. Many engineers have to use other methods to find the cause, which is time-consuming and laborious.

　　Now we will use a real case to illustrate the function of the timing analysis function of the logic analyzer in hardware debugging. It is particularly important to note that the virtual logic analyzer used in this example is based on USB.

　　Address Counter

　　4-bit address AB3-0

　　clock

　　RAM

　　data input

　　data input

　　Data Output

　　Figure 1. Schematic diagram of a four-bit memory

　　Figure 1 is a schematic diagram of a faulty memory circuit. The fault phenomenon is that the stored data and the read data are different, which is a hardware fault. First, use the timing analysis of the logic analyzer to observe the write clock added to the RAM and the 4-bit address generated by the address counter. First, let's analyze the timing process of its operation:

　　The clock provides a reference for reading and writing data with a 4-bit address, and the timing of the action is determined by a logic control signal.

　　From the analysis of Figure 1, it can be seen that the suspicious point may be the clock signal or the 4-bit address counter. From Figure 2, it can be seen that the write clock (i.e. the "clock Φ" in the figure) appears periodically. Under the action of the write clock, the address counter counts and outputs different addresses for RAM use. The logical relationship on the left side of the white box in Figure 2 is correct, but in the white box part of the figure, it can be clearly found that when the write clock is not in effect, the address counter still counts in reverse, resulting in a logical error. This leads to read and write errors.

Figure 2. Abnormal four-bit address memory timing diagram

　　Why does the address counter work when there is no clock edge? Experienced engineers know that this is related to glitches. Use a hook to connect these 5 signal lines (4-bit address lines + 1-bit clock line) to the TWLA500 host. Because it is a virtual instrument, the TWLA500 must be connected to the PC first. As shown in Figure 4. The order and names of the 5 channels can be defined by yourself.

Figure 3. Timing diagram of read and write anomalies

　　In this example, channel 3 is the clock signal, and the trigger word can be flexibly selected, for example, address 0000 can be selected for triggering. You can also set the trigger delay and adjust the sampling period appropriately to make the entire signal complete and clear on the screen. The timing diagram is shown in Figure 5.
 

Figure 4. Connection of TWLA500 to the circuit

　　You can also use advanced triggers, such as setting a trigger when an abnormal jump occurs. The actual working signal captured by the logic analyzer is shown in Figure 5.

Figure 5. Circuit operation signal captured by TWLA500

　　After further amplification, it is found that the clock signal has a glitch at about 15.5uS. (As shown in the red box in Figure 6)

Figure 6. The glitch signal is magnified and its true colors are revealed.

　　As shown in Figure 6, at the moment of the false reversal, the clock signal has a burr (red box in Figure 6). This causes a read/write error. TWLA500 captures and finds that the burr cycle is very short, with a gap of several nS. It is difficult for ordinary logic analyzers to capture this burr. Because the sampling rate of TWLA500 is as high as 500M and the Setup/Hold Time is ≈ 0nS, it is easy to capture this burr. Continuing to track, it can be found that the root cause of the clock burr is the existence of equivalent capacitance and resistance in the circuit. During operation, the RC has charging and discharging phenomena, which causes the clock signal to be unstable at the edge of the jump. This provides strong support for hardware engineers to finally find the root cause of the fault.

Logic Analyzer + Clock Generator

　　From the above examples, we can see that logic analyzers are very useful tools in digital systems. Especially as their functions become more abundant and their prices decrease, logic analyzers will play an important role in the revolution of digital systems in the long run.