Design of digital frequency meter based on VHDL language

　　Digital frequency meter is an indispensable measuring instrument in the production fields of communication equipment, computers, electronic products, etc. As the number of devices in hardware design increases, the design becomes more complex, the reliability deteriorates, the delay increases, and the measurement error becomes larger. By using EDA technology to describe the system functions and using VHDL language, the system is simplified to improve the overall performance and reliability. The digital frequency meter designed with VHDL programming, except for the shaping part of the measured signal, key input and digital display, is implemented on a FPGA, making the entire system very streamlined and flexible to change on site. On the basis of not changing the hardware circuit, the system performance is further improved, so that the digital frequency meter has the advantages of high speed, high accuracy, strong reliability, and anti-interference, creating conditions for further integration of digital systems.

　　2. Working principle of digital frequency meter

　　Among the frequency measurement methods, the commonly used ones are direct frequency measurement method, frequency doubling method and equal precision frequency measurement method. In the direct frequency measurement method, the measured frequency signal is added to the input end of the gate according to the meaning of frequency. Only within the gate opening time T (measured in ls), the measured (counted) pulse is sent to the decimal counter for counting. The direct frequency measurement method is simpler, more convenient and more feasible than the other two schemes. Although the direct frequency measurement method has a large error when measuring in the low frequency band, we can use the direct cycle measurement method to measure in the low frequency band, which can improve the measurement accuracy. The direct cycle measurement method is to directly control the counting gate circuit with the measured cycle signal, so that the main gate opening time is equal to Tx, and the pulse with the time mark Ts enters the counter during the main gate opening time. Assuming that the count value during Tx is N, the measured signal period can be calculated according to Tx=N×Ts. Therefore, this paper adopts the low-frequency cycle measurement and high-frequency frequency measurement methods to improve accuracy and reduce errors.

　　3. Implementation of main functional modules

　　The controller designed in this system is realized by a state machine. By selecting a reasonable time base signal frequency in different measurement gears to reduce the error, determine the conditions and state names of each state transfer, and use the method of measuring the cycle in the low-frequency gear and the frequency in the high-frequency gear. The 20MHz crystal oscillator is sent to the divider to separate the time base signal of each gear and the trigger signal required by other modules. The divider transmits the time base signal of each gear to the state machine. At the same time, the signal to be measured enters the state machine, and the state machine performs state conversion, and the range overflow signal and the state display signal are represented on the light-emitting diode . As shown in Table 1.

　　3.1 State Machine Module

　　First, reset the system. If the initial state of the state machine is F100k, if an over-range signal is sent to the state machine, the state is converted to F1M. If there is still an over-range signal, the state is converted to F10M. If there is still an over-range signal, the state is converted to F100M. If there is still an over-range signal, the state is converted to Overflow H to generate a high overflow signal. If an under-range signal is sent to the state machine, the state is converted to P1ms. If there is an over-range signal, the state is converted to P10ms. If there is still an over-range signal, the state is converted to P100ms. If there is still an over-range signal, the state is converted to P 1 s. If there is still an over-range signal, the state is converted to OverflowL to generate a low overflow signal. As shown in Figure 1.

　　3.2 Counter module

　　The transmission of the counting and control signals (Over and Low) is completed within two clock cycles of the "signal to be counted", and the count value is output if the range is appropriate. Within these two clock cycles, the first clock cycle completes the counting, and the second clock cycle completes the transmission of the control signal and the output of the count value. The advantage of this is stability, and the counting and control signal transmissions are separated. This avoids some "clock jumps" that may be encountered. However, the disadvantage of this approach is also obvious, that is, in the measurement cycle mode, if the signal to be measured is 1Hz, then the system may need 2s (two clock cycles) to display the correct value.

　　3.3 Ten-frequency module

　　Since it is not feasible to measure the signal of 1kHz~10kHz using either the frequency measurement method or the period measurement method, the pre-division method can be used to divide the signal of 1kHz~10kHz into ten parts, and then the period measurement method can be used to measure the period and then calculate the frequency.

　　3.4 Synchronous Shaping Circuit Module

　　The external asynchronous signal, over-range and under-range are processed by the synchronous shaping circuit. The source program is as follows:

　　library ieee;use ieee.std_logic_1164.all;entity SignalLatch is4. Functional simulation and verification analysis of the system.

　　According to the state transition diagram, the state machine program is divided into two processes. Process 1 completes the state transition process, and process 2 controls the output value in each state as shown in Figure 2 below. timecounter=clocktested is 50KHz.

　　For the convenience of observation, the value is changed to a smaller value, and the count value is output when it is greater than 100 and less than or equal to 1000! Set clock1 to 50K, and clock2 to 5M. The simulation result is shown in Figure 3. The result is 100, which meets the counting requirements.

　　As shown in Figure 4, clk1 is given a frequency of 5KHz, and after ten times the frequency is increased, clk2 outputs 0.5KHz. The period of clk1 is 0.2ms, and after ten times the frequency is increased to 2ms.

　　The synchronous shaping circuit simulation is shown in Figure 5.

　　The frequency measurement is obtained by simulating the above modules, as shown in Figures 6, 7, and 8.

　　5 Conclusion

　　The digital frequency meter designed in this scheme occupies less FPGA chip resources, has low cost, reduces the size of the circuit, and has certain practical value. The simulation and hardware testing were carried out using the QuartusII platform, and basically met the design requirements. This proves that this scheme has good reliability, flexibility and practicality.