Comprehensive understanding of logic analyzer (Part 2)

The logic analyzer acquires data stored in memory in real time and can be used in a variety of display and analysis modes. Once the information is stored in the system, it can be viewed in a variety of formats, from timing waveforms to instruction mnemonics associated with the source code.

The waveform display is a multi-channel detailed view that allows the user to see the time relationship of all captured signals, much like an oscilloscope display. It is commonly used for timing analysis and is particularly suitable for:

• Diagnose timing problems in the SUT hardware.

• Compare the recorded results with the simulator output or the timing diagrams in the data sheet to verify that the hardware is operating correctly.

• Measure characteristics related to hardware timing, including race conditions, propagation delays, and the absence or presence of pulses.

Analyzing burrs

The Lister display provides status information in a user-selectable alphanumeric format. The data values ​​in the list are derived from samples captured across the bus and can be expressed in hexadecimal or other formats. Imagine taking a vertical "slice" through all the waveforms on the bus. A slice through the 4-bit bus represents a sample stored in real-time acquisition memory. As shown in Figure 5, the number in the shaded slice is what the logic analyzer will display, usually in hexadecimal. The purpose of the Lister display is to show the status of the SUT, allowing you to see the information the way the SUT sees it.

5. State acquisition captures a “slice” of data on the bus when an external clock signal enables acquisition.

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State=011 binary=7 hexadecimal: State=011 binary value=7 hexadecimal value

Status data is displayed in a variety of formats. Real-time instruction trace disassembles each bus transaction to determine which instructions were read on the bus. It places the corresponding instruction mnemonics on the logic analyzer display along with the associated addresses.

There is also a source code debugging screen, which improves debugging efficiency by associating the source code with the instruction trace history. It can instantly view the actual working status of the instruction execution. The source code screen can be associated with the real-time instruction trace.

With the help of the processor-specific software package, state analysis can be displayed in mnemonic form. You can debug software problems in the SUT more easily. Equipped with this knowledge, you can enter a lower-level state display (such as hexadecimal display) or enter a timing diagram display to track down the source of the error.

The automatic measurement function can perform comprehensive measurements on the logic analyzer acquisition data. A large number of oscilloscope-like measurements are available, such as frequency, period, pulse width, duty cycle, and edge count. The automatic measurement function quickly provides measurement results with a large sample capacity, achieving fast and comprehensive results.

The following two usage scenarios illustrate how a logic analyzer can be used to solve common measurement problems.

Capturing setup or hold violations

Setup time is the minimum time that the input data must be valid and stable before the clock edge shifts it into the device. Hold time is the minimum time that the data must be valid and stable after the clock edge occurs. Digital device manufacturers specify setup and hold time parameters, and engineers must pay special attention to ensure that the design does not violate the specifications.

However, today's tighter tolerances and widespread adoption of faster parts to drive higher throughput have made setup and hold violations increasingly common. In recent years, setup and hold requirements have narrowed to the point where the events are difficult to detect and capture with most traditional general-purpose logic analyzers. The only real solution is a logic analyzer with nanosecond sampling resolution.

The following example uses synchronous acquisition mode, relying on an external clock signal to drive the sampling. In either mode, the logic analyzer provides high-resolution sample data buffering around the trigger point. In this case, the DUT is a "D" flip-flop device with a single output, but this example is also applicable to devices with hundreds of outputs.

In this example, the DUT itself provides the external clock signal, which controls the synchronous acquisition. You can use the logic analyzer drag-and-drop triggering function to create a setup and hold trigger. This mode allows you to define setup and hold violation parameters (Figure 6). You can use other submenus in the setup window to refine other aspects of the signal definition, including logic conditions and positive or negative terms.

6. You can define setup and hold violation event parameters to create triggers.

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While the test is running, the logic analyzer actually evaluates every rising edge of the clock to identify setup or hold violations. It monitors millions of events and captures only those that fail to meet setup or hold requirements. Figure 7 shows the resulting display. Here, the setup time is 2.375 ns, well below the specified limit of 10 ns.

7. After the logic analyzer evaluates each rising edge of the clock, it displays setup and hold violations.

Signal Integrity

Visually observing and measuring signals is the only way to discover problems related to signal integrity. For the most part, the same instruments that are familiar to people in almost any electrical engineering lab are used to measure signal integrity. These instruments include logic analyzers and oscilloscopes, as well as probes and application software that complete the basic tool box. In addition, signal sources can be used to provide distorted signals, perform stress tests, and evaluate new devices and systems.

When debugging digital signal integrity issues, especially in complex systems with large numbers of buses, inputs, and outputs, a logic analyzer is the first line of defense. It offers high channel counts, deep memory, and advanced triggering to acquire digital signals from multiple test points and then display the information in a coherent manner. Because it is a digital instrument, a logic analyzer detects threshold crossings on the signals it monitors and then displays the logic signal as the logic IC sees it.

The resulting timing waveforms are clear and understandable, and they can be easily compared to expected data to confirm that everything is working properly. These timing waveforms are often the starting point for searching for signal problems that compromise signal integrity. These results can be further interpreted with the help of disassemblers and processor companion software packages, which allow the logic analyzer to correlate real-time software traces (associated with source code) with low-level hardware activity (Figure 8).

8. This logic analyzer display shows timing waveforms and real-time software traces associated with source code.

However, not every logic analyzer is suited for performing signal integrity analysis at today's extremely high (and increasing) digital data rates. The following table provides some technical data guidelines that should be considered when selecting a logic analyzer for advanced signal integrity debugging. With all the emphasis on sampling rate and memory capacity, it is easy to overlook the triggering capabilities in a logic analyzer.

Triggers are often the fastest way to find problems. After all, if the logic analyzer triggers on an error, then it has proven that an error has occurred. Most current logic analyzers include a variety of triggers that can detect specific events that compromise signal integrity, such as glitches and setup and hold violations. These trigger conditions can be applied to hundreds of channels at once, which is a unique advantage of logic analyzers.

summary

Logic analyzers are essential for digital debugging at all levels. As digital devices have gotten faster and more complex, logic analyzers have evolved to keep pace. They provide the speed to capture the fastest, most transient anomalies in a design; the capacity to observe all channels at high resolution; and the memory depth to unravel the relationships between dozens, hundreds, or even thousands of signals over multiple cycles.

Triggering can confirm a suspected problem or reveal a completely unexpected error. Most importantly, triggering provides a wide variety of tools to test hypotheses related to a fault or to define intermittent events. The array of trigger options in a logic analyzer is a hallmark of its versatility. In addition, the high-resolution sampling structure can reveal invisible details related to the characteristics of the signal.

Using a single probe to simultaneously acquire state data and high-speed timing data can help designers collect a large amount of data about their devices and then analyze the relationship between timing diagrams and high-level state activity. Other features such as acquisition memory, display and analysis capabilities, integrated simulation tools, and even modularity combine to make logic analyzers the tool of choice for finding digital problems and meeting tight design schedules.

      Logic Analyzer Requirements for Signal Integrity Testing