Teach you how to test USB3.0 receiver step by step

The goal of USB receiver testing is to confirm that the receiver can correctly detect transmitted data at a target bit error rate (BER) of 1x10-12 or less. While transmitter testing focuses on amplitude, jitter, or other parameter measurements, receiver test strategies typically involve one test: jitter tolerance. Jitter tolerance ensures that the receiver system will interoperate with other products with a high degree of confidence. Interoperability conditions can vary widely with factors such as different cable lengths, low signal amplitudes, asynchronous reference clocks, power management link states, etc. A good stressed eye calibration method will ensure that jitter tolerance reaches as many potential conditions as possible.

USB 3.0 compliance testing has changed significantly to accommodate the new challenges associated with the higher speed interface. Validating USB 2.0 receivers requires performing receiver sensitivity testing. High-speed devices must respond to test packets at or above 150 mV and ignore (squelch) signals below 100 mV. SuperSpeed ​​USB receivers must support significantly more signal impairments, so the testing requirements are more stringent than USB 2.0. Although the USB 3.0 specification specifies a target BER of 1x10-12, receiver compliance test strategies can increase deterministic jitter to produce an effective BER of 1x10-10, allowing for shorter test times. This results in equivalent Tj(BER) for both target BER levels at the lower BER, due to the increased Dj and lower effective Rj. For USB 3.0 testing, there are multiple test options to fully evaluate USB 3.0 Rx devices.

Tektronix allows customers to choose between two solutions to automate receiver testing for USB 3.0. For characterization testing, which is typically used for first draft silicon, an instrument such as the BERTScope can be used. The BERTScope Bit Error Rate Analyzer provides the functionality of an enhanced high-performance Bit Error Rate Tester (BERT) with the eye diagram display capabilities of an oscilloscope. For test scenarios that require dynamic changes to parameters such as data rate, jitter configuration, or data pattern, the BERTScope provides universal pattern generation and BER-based debug tools to support the full set of measurements required for USB 3.0 Rx testing.

For compliance testing that often requires full automation, a test platform using an arbitrary waveform generator (AWG), a Tektronix DPO/DSA/MSO70000 Series oscilloscope, and TekExpress automation software may be the best solution. The AWG7122 can emulate serial data streams, signal impairments, and compliance channels simultaneously, significantly simplifying test configuration. The DPO/DSA/MSO oscilloscope provides error detection capabilities and automatic configuration control when equipped with a bit error rate detector (Option ERRDT). Both instruments are controlled by TekExpress software, which provides a simple and efficient way to automatically test USB 3.0 transmitter/receiver hosts and devices that meet the requirements of the Electrical Interface Compliance Test Specification (CTS).

Receiver verification and commissioning tests

The main basis for evaluating a receiver is to determine the effective bit error rate. A known pattern is transmitted to the receiver and the data is verified after the receiver's comparator. The data is verified externally through a loopback mechanism inside the receiver. One of the challenges of receiver testing is to generate the required test pattern to initiate the test mode inside the device under test.

USB 3.0 receiver testing is similar to other high-speed serial bus receiver compliance testing and is generally divided into two stages:

< Stressed Eye Calibration is the industry name for creating a worst-case signal condition to test a receiver. This worst-case signal is usually impaired by adding jitter horizontally and setting the amplitude vertically to the lowest amplitude the receiver will see when deployed. Stressed Eye Calibration must be performed with any test fixture, cabling, or instrumentation changes.

< Jitter tolerance tests the receiver using a calibrated stressed eye as input, then applies additional sinusoidal jitter (SJ) of increasing frequency. This applied SJ tests the clock recovery circuitry inside the receiver, so not only is the receiver tested with worst-case signal conditions, but it also explicitly tests its clock recovery. The amplitude and frequency of the applied SJ adheres to a template specified by the standard. This jitter tolerance template covers the bandwidth of the clock recovery PLL, and high amounts of applied SJ should be tolerated within the loop bandwidth, as the clock recovery will track out this sinusoidal jitter, but only small amounts can be tolerated above the loop bandwidth, as this jitter is not tracked out and will affect the downstream receiver circuitry.

This verification process can be automated to ensure accurate structure and correct stressed pattern generation capabilities. The following is an overview of the automated verification capabilities:

< Loopback Initiation provides testing capabilities for users who would not otherwise be able to perform receiver testing. Loopback Initiation is a specific handshake between the BERTScope and the device under test (DUT) that prepares the DUT for receiver testing. This is a critical step that is a challenge for many customers regardless of the test instrument used.

< Automatic stressed eye calibration simplifies an otherwise tedious and time-consuming procedure.

< Jitter tolerance testing can be performed with a single click and the results are stored in a database for concise management of test results. Automated jitter tolerance testing can also search for device limits, a function called "Search Margin".

Figure 1. Stressed Eye calibration using the BERTScope BSA Series.

Stressed Eye Calibration

Three impairment calibrations must be performed to calibrate for stressed eye, random jitter (RJ), sinusoidal jitter (SJ), and eye height. Each calibration requires specific setup on the Tektronix BSA Series pattern generators and analyzers, and measurements are performed using the Tektronix MSO/DSA/DPO70000 Series oscilloscopes.

1. Random Jitter (RJ)

< Definition: RJ is unbounded jitter and is independent of the data pattern, that is, the measurement should be the same regardless of the data pattern. Since RJ is unbounded, it increases with the measurement depth, and the deeper the measurement, expressed in terms of the number of waveforms being measured, the greater the peak-to-peak RJ measurement result.

< How to adjust: To achieve the correct amount of RJ, the pattern generator must be able to adjust the amount of RJ injected.

< How to measure: MSO/DSA/DPO70000 Series oscilloscopes equipped with DPOJET can provide automatic RJ measurements.

2. Sinusoidal Jitter (SJ)

< Definition: SJ is bounded jitter that is periodic in nature but is usually uncorrelated with the data pattern (unless the SJ frequency is an exact multiple of the pattern repetition rate), so like RJ, the measurement is the same regardless of the data pattern. Unlike RJ, it does not increase with measurement depth due to its bounded nature.

< How to adjust: As with RJ, the pattern generator must be able to adjust the amount of SJ injection to achieve the desired amount. The injected SJ must be of a specific frequency and have adjustable amplitude. All SJ frequencies and amplitudes must be calibrated within the USB 3.0 jitter tolerance template.

< How to measure: The USB 3.0 compliance test procedure states that the amount of SJ should be measured by taking the difference between the total jitter (TJ) of a signal with zero SJ amplitude injected and the desired amount of SJ injected. The DPOJET analysis option of the Tektronix MSO/DSA/DPO 70000 Series oscilloscopes provides TJ measurements.

3. Aim high

< Definition: Eye height is the degree of eye opening at the center of the unit interval and is measured at a depth, in this case 106 waveforms. Eye height is data pattern dependent as it is affected by the amount of data dependent jitter (DDJ) in the signal. Eye height specifications are different for the host (180 mV) and the device (145 mV).

< How to adjust: The eye height is adjusted by the output amplitude of the BERTScope pattern generator.

< How to measure: Eye height can be measured on Tektronix MSO/DSA/DPO70000 series oscilloscopes.

Jitter Tolerance Test

Once the stressed eye is calibrated, receiver testing can begin. As mentioned in the Introduction, USB 3.0 requires BER testing, unlike the previous generation specification 2.0. Bit error rate (BER) testing in the form of jitter tolerance testing is the only test required for USB3.0 receiver testing and can be performed using the Tektronix BERTScope BSA Series analyzer.

Jitter tolerance testing tests the receiver using worst-case input signal conditions (the stressed eye calibrated in the previous section). On top of the stressed eye, a range of SJ frequencies and amplitudes covering the frequency range around the JTF -3 dB cutoff frequency are injected into the test signal, and the error detector monitors the receiver for errors or bit errors, calculating the BER. [page]

Figure 2. USB 3.0 receiver test setup.

The equipment setup for receiver testing is similar to stressed eye calibration, with the DUT inserted into the test loop. However, instead of feeding the signal directly back into the analyzer, the test signal from the pattern generator flows through the DUT's receiver, "loops back" through the transmitter (hence the name), and then back through the adapter to the error detector. The connection to the error detector should be as high quality as possible. (See Figure 2)

For jitter tolerance testing, the test instrument must be able to perform bit error detection and track the BER. Instruments such as BERTs, some protocol analyzers, and oscilloscopes have this capability.

Loopback is a USB 3.0 link state in which the device sends the bits it receives back to the transmitter. If errors occur at the receiver, the errors are sent back to the transmitter and to the downstream analyzer for detection. To initiate loopback, a series of handshakes must be performed between the pattern generator and the DUT.

USB 3.0 uses 8b/10 encoding, and as is common in 8b/10b encoded systems, the receiver and transmitter may be at slightly different clock frequencies, and the clock recovered from the received data stream may not be exactly equal to the transmitter clock frequency. This frequency mismatch can cause problems for the DUT in receiver test loopback mode, where bits may come in faster than they are sent back, or vice versa. To compensate for the frequency mismatch, clock compensation symbols can be used, which are either removed or inserted into the data stream when transmitted back from the receiver to the transmitter. For example, if the recovered clock frequency is less (slower) than the transmitter clock frequency, then symbols should be added, and vice versa. USB 3.0 uses SKP symbols for clock compensation.

The BERTScope BSA Series can be set up to handle this undetermined number of clock-compensated symbols in the incoming data stream, commonly referred to as asynchronous BER testing. This can be difficult with some BERTs, as BER is typically measured by comparing the incoming data stream to a known data pattern. A protocol analyzer may be able to handle this test mode by keeping count of the number of frame errors.

Finally, note that the USB 3.0 specification includes two types of loopback for BER testing. The first is as described above, where the received bits are retransmitted back to the analyzer for BER testing. The second relies on the DUT to track its own BER and report this value back in bits embedded in a special pattern called an ordered set. However, the latest compliance test specification does not include the second method.

Once the stressed eye has been calibrated, the DUT and equipment have been set up for test, and the DUT has been placed in loopback mode, you are ready to test the DUT's receiver.

Jitter tolerance testing applies different SJ amplitudes at specific SJ frequencies to test the receiver. In general, the lower the SJ frequency, the higher the SJ amplitude will be, because these frequencies fall well within the loop bandwidth of the receiver clock recovery and can therefore be tracked. As the SJ frequency approaches and exceeds the loop bandwidth, the SJ amplitude will flatten out at an amplitude less than 1 UI. Jitter above the receiver loop bandwidth will not be tracked and will be transmitted back to the receiver's decision circuitry.

The USB 3.0 CTS specifies that each SJ point on the tolerance curve should be tested using 3x1010 bits. If more than one error is detected at any SJ test point, the DUT test fails.

For proper USB 3.0 receiver testing, the test regime is completely based on jitter tolerance using calibrated stressed eye inputs. For receiver characterization and debugging, the BERTScope BSA Series combines calibrated stressed eye setup with automated features to ensure a successful receiver test and debug environment.

For compliance testing, the Tektronix AWG7000 combined with a Tektronix oscilloscope and TekExpress automation software provides a solid choice.

Figure 3. USB 3.0 receiver characterization test setup for loopback BER.

Figure 4. Detecting frame errors using an AWG and oscilloscope.

Receiver Compliance Testing Using an AWG

The primary basis for characterizing a receiver is to determine the effective bit error rate. Using the automated capabilities of a pattern generator such as the AWG7000, a known pattern is sent to the receiver and the data is checked after the receiver comparator. The data is checked externally through the receiver's internal loopback mechanism. One challenge in receiver testing is generating the required test patterns to initiate test modes within the device under test. These test patterns involve forcing the transmitter to "repeat" the detected data, which is then sent out through the transmitter after retiming, and then invoking the internal error detection state. The advantage of an arbitrary waveform generator (AWG) is the ability to sequence through the required link training, enter the receiver loopback, and issue the loopback bit error rate test (BERT) command. Figures 3 and 4 show an example of the flow of testing a host using the loopback BERT method in both test initiation and error detection as the AWG sequences through the following steps. The Tektronix DSA70000 real-time oscilloscope can acquire and decode the number of bit errors sent by the receiver. [page]

In addition to the internal BERT method, external error detection can be used to characterize the receiver. USB 3.0 requires different reference clocks between the host and device, which results in different local clock speeds. SKP ordered sets are used to compensate for clock timing offsets within the link. Temporary buffering of symbols by the receiver is handled using an elastic buffer. The elastic buffer must be deep enough to handle extreme clock differences, including the effects of SSC. Since the maximum frequency range allowed between the host and device is +/-300 ppm, taking into account the effects of SSC (0 to -5000 ppm), this results in a maximum frequency offset range of +300 to -5300 ppm. As mentioned earlier, USB 3.0 receivers include internal error detection. Internal error detection provides an economical solution for performing receiver testing. However, it has a limitation in that it has poor flexibility in the use of patterns, as only the CP0 pattern (scrambled D0.0) supports pattern recognition. It is possible to test other patterns, such as CJTPAT or PRBS patterns, using external error detection, provided that the error detector supports the pattern used. To verify the external loopback, there are two methods: synchronous error detection and asynchronous error detection. Synchronous error detection means that the pattern generator and the error detector are timed to a common reference clock, so the receiver is evaluated bit by bit. Asynchronous error detection does not require a reference clock and symbol error detection can be performed by removing or inserting idle characters (such as SKP). An error detection instrument is a protocol analyzer that, in addition to error detection, can also perform various other functions, such as traffic monitoring, emulating a host, and performing link training.

Channel Simulation and Automation

Due to 5 Gb/s signaling, long host channels and cables, this results in eye closure at the receiver, requiring equalization. Test specification developers specify channel requirements that are both capable of performing tests based on worst-case conditions and practical enough to allow engineers to design and manufacture products in a cost-effective manner. After the channel model and budget are created, the product is verified to ensure that the actual physical layer performance matches the expected results. Software simulation tools provide many degrees of freedom to quickly model and test corner cases. But at some point, the model must be generated into the physical channel to be verified. Usually the reference design is built on a PCB that provides electrical characteristics similar to the specification.

Another way to create a channel model in hardware is to convert the model into a differential S-parameter file and convolve the channel with the test pattern from the signal generator, including amplitude and phase effects. This approach allows engineers to drive the device under test with specific channel requirements that are not only variable but also repeatable. There are several software tools on the market, such as Tektronix SerialXpress and BERTScope BSAUSB3, that can automatically generate complex signals for USB 3.0 receiver testing by integrating all impairments into a single signal. Complex jitter components such as Rj, Sj, ISI, custom SSC modulation configurations, fine-grained ISI scaling (such as 12-inch vs. 12.1-inch PCB traces), and pre-emphasis can be added simultaneously to create complex channel models often seen in real-world environments. Figures 5 and 6 illustrate an example of unified pattern generation and device control using USB3 receiver automation tools.

Figure 5. SerialExpress setup screen for the AWG7000.

Figure 6. BSAUSB3 automated software setup screen.

Channel Measurement

Conformance Testing

At 5 Gb/s data rates, anything that affects signal rise time, pulse width, timing, jitter, or noise content will impact system-level reliability. To ensure signal integrity, it is necessary to understand and control the impedance and losses in the transmission environment through which the signal flows. Mismatches and variations can cause reflections and overall degradation of signal quality. USB 3.0 channel compliance testing helps eliminate potential sources of performance degradation. The following is a list of required USB 3.0 channel measurements. The DSA8200 sampling oscilloscope, 80E04 TDR module, and IConnect measurement software and A/B socket test fixture provide a complete channel compliance test solution.

1. Impedance

2. Internal latency

3. Differential Insertion Loss

4. Differential return loss

5. Differential Near-End Crosstalk

6. Differential crosstalk between USB3.0 pairs and USB2.0 pairs

7. Differential to Common Mode Conversion

Figure 7. DSA8200 sampling oscilloscope with IConnect TDR/S-parameter measurement software installed. [page]

Figure 8. TDR reveals impedance discontinuities.

Figure 9. The 4x4 matrix describes the formula system for calculating 4-port S-parameters.

Figure 10. Differential and common-mode stimulus and response.

Verification and debugging

Impedance measurements are relative and are made by comparing the reflected amplitude to the incident amplitude. Modern TDR instruments perform all the calculations comparing the incident and reflected amplitudes to the reported rho (reflection coefficient) or ohms. Figure 8 shows the change in impedance relative to the characteristic impedance, Z0, as the incident TDR step moves from the connector to the end of the trace and then to the open circuit. Note that the accuracy of this process is highly dependent on the reference impedance of the TDR source, in this case Z0.

S-parameters (scattering parameters) are becoming increasingly common in describing frequency domain network performance. They are defined by incident and reflected waves at each port and describe the power or voltage present as a function of frequency. Figure 9 shows the single-ended incident and return voltages relative to each port. Figure 10 illustrates a popular measurement configuration, which performs measurements in differential mode. Mixed-mode S-parameter measurements, including differential and common-mode measurements, provide an advantage in providing insight into potential signal integrity issues. Differential measurements are directly related to signal attenuation because the majority of the signal energy propagates in this mode. Common-mode measurements are related to delay and ground bounce. Mode conversions can cause electromagnetic interference (Diff-CM) and electromagnetic susceptibility (CM-Diff). Finally, cross-coupling between adjacent lines can cause crosstalk. Both impedance and S-parameter measurements are critical to designers, as these tools can identify potential signal integrity issues. In the time domain, TDR can isolate impedance discontinuities and even correlate simulation models with physical measurements. In the frequency domain, S-parameters essentially provide a transfer function representation or relative behavioral model.

USB 3.0 measurements that can be made using a TDR include differential impedance, frequency domain crosstalk, and S-parameters, including Sdd21 insertion loss and differential to common mode conversion. These measurements are made using a 45 ohm reference impedance or a 90 ohm differential impedance. Since most TDR systems use a 50 ohm reference impedance, the measured data needs to be normalized in software to the target 90 ohm differential reference impedance.