How to Verify and Analyze Complex Serial Bus Link Models

Faster signal transmission speeds and shrinking geometries require powerful data link applications to support live waveform modeling, measurement, and simulation on real-time oscilloscopes. On the design side, there is a trend to use advanced equalization techniques at transmitter and receiver locations to address these challenges. Smaller form factors make signal access more difficult and create non-ideal probing points. This results in losses and reflections when acquiring signals due to impedance discontinuities that do not exist at the ideal measurement location.
 

The Serial Data Link Analysis application allows users to load a circuit model of the measurement circuit, which includes the test and measurement fixtures and the instruments used to acquire the DUT (device under test) waveform. This helps de-embed the losses and reflections caused by the fixture and test equipment (such as probes and oscilloscopes) from the acquired waveform. De-embedding these effects can improve measurement accuracy and is sometimes directly related to the pass or fail of the test. In addition, the Link Analysis application allows users to define simulation circuits by loading channel models for serial data link systems to evaluate performance without using actual link hardware.

A typical use case is to capture waveforms of the actual transmitter circuit to be evaluated through a fixture. This allows observation of transmitter waveforms without the measurement circuit and simulating an ideal load. At the same time, the serial data link fidelity model can also be connected to the transmitter (TX) to evaluate the far-end signal, while the receiver (RX) model can be simulated using the continuous time linear equalizer (CTLE), feedforward equalizer (FFE) and decision feedback equalizer (DFE) or RX IBIS-AMI model. Signal simulation can therefore be performed at any test point in the link, resulting in live waveform output that can be used in other applications to measure signal quality, including jitter and eye diagram analysis.

An example of this modeling setup is shown in Figure 1. The system acquires an input waveform from an oscilloscope and applies a transfer function to the acquired signal to obtain the test point waveforms. These test points allow the user to view the waveform at any point in the link and display it as a live waveform on the oscilloscope display.

Figure 1: The Serial Data Link Analysis Visualizer application enables real-time measurement circuit de-embedding, serial data link component simulation, and live waveform equalization in a real-time oscilloscope.

Ensure adequate test margin

随着数据传输速率从5Gb/s向10Gb/s及更快水平迈进，每一ps和mV对确保充足的测试余量都很重要。目标是测量DUT而非用于采集信号的测试设备、夹具或电缆。例如，消除SMA电缆的效应可显著改善器件的余量。信号频率越高，效果越显著。

In the example below, an 8Gb/s PRBS7 signal is acquired using an SMA cable through an SMA connector soldered directly onto a test board. The goal is to remove the effects of the SMA cable from the test board. These effects include the losses through the cable and any reflections due to impedance mismatches in the cable and the cable connectors. Before the cable effects can be de-embedded, the measurement circuit must be known. This includes knowing the TX output impedance, the cable model, and the input impedance of the receiver (i.e., oscilloscope). For simplicity, it is assumed that both the TX output and RX input impedances are nominally 50Ω. Using a TDR or VNA, an S-parameter model of the SMA cable can be obtained, which can be used in the de-embedding process.

Using the Serial Data Link Analysis software, the S-parameters of the cable are set in the de-embedding module and the test point Tp2 is enabled. The end result is a waveform with the SMA cable effect removed. The reflection and transmission terms can be quickly verified using the curves shown in Figure 2. The reflection coefficients are represented by S11 and S22, and the transmission terms are represented by S21 and S12. For passive circuits, the forward and reverse transmission terms are exactly the same, as shown in the example in Figure 2. If they are not the same, it indicates that there is an error in the measurement.

In this example, each lead of the SMA cable is represented by two separate 2-port S-parameter models.

Figure 2: The figure above is a frequency domain 2-port S-parameter plot showing the transmission and reflection terms of the SMA cable. For passive circuits, as in this example, the forward and reverse transmission terms are exactly the same.

Although the cable loss is only 1dB at the 4GHz fundamental frequency, this still equates to a reduction of approximately 10% in the high frequency content of the signal. It is also clear that as the signal frequency increases, the loss also increases, demonstrating the impact of the cable on the DUT margin.

The time domain impulse response plot for each of the above S parameter vectors is shown in Figure 3. This is also a useful view because it shows the delay of the transmission terms. It also shows whether the data was created within the time interval, because otherwise the validity of the S parameter set cannot be guaranteed. These curves are obtained by calculating the IFFT (Inverse Fast Fourier Transform) of the frequency domain S parameter data. This often requires extrapolating the frequency domain data to DC, and sometimes to the higher ideal Nyquist frequency. [page]

Figure 3: The time domain plot of the 2-port S-parameter model of the SMA cable is also a useful view because it shows the delay of the transmission terms.

Taking the start-up voltage of a PCI Express 3.0 device as an example (which is required to be 800mV-1300mV at the transmitter pin), a 10% improvement is equivalent to a 10mV margin. Figure 4 shows the waveform analysis results before and after de-embedding the SMA cable. Note the difference in the eye height and rise time of the signal.

Figure 4: Comparison of the acquired signal before and after de-embedding the SMA cable shows improvements in the signal’s eye height and rise time.

To generate the eye diagram on the right (Figure 4), a transfer function was applied to the acquired waveform. This is the result of calculating the effects of the DUT, SMA cable, and receiver. The transfer function for each test point can be plotted using the Link Analysis software. In some cases, it is helpful to observe the loading effects of the measurement circuit on the DUT. Enabling Tp1 allows a simultaneous view of the signal with and without the loading effects of the measurement circuit. Figure 5 shows the transfer function at TP1 and TP2. Note that the small ripple in the transfer function at TP1 is due to the loading effect of the SMA cable. The phase, step, and pulse responses can also be observed for each test point.

Figure 5: This example shows a FIR filter transfer function curve for an SMA cable. This can be used to observe the loading effects of the measurement circuit on the DUT.

RX Characterization

Another common use case is characterizing the DUT at the far end or RX side. In the past, the signal might have been acquired and measured directly, but as data rates have increased, the eye is now closed at the far end, making RX equalization a necessity. RX equalization is used to open the eye of the acquired signal so that it can be characterized and analyzed. Analysis capabilities may include parametric measurements, jitter and eye measurements, or protocol decoding.

There are various methods for RX equalization, including CTLE, FFE, or DFE. Because most next-generation specifications are "closed-eye" cases, it is common practice to specify a reference equalizer. For example, PCI Express 3.0 requires a CTLE+1-tap DFE, which is the same requirement for the new version USB SuperSpeed. This equalizer is often used for compliance testing and receiver calibration, but is not intended to define how equalization is implemented in silicon chips.

The use of a reference equalizer is sufficient for compliance testing, but in many cases, system designers need to characterize their system using their channel with a dedicated silicon model. In this case, accurate modeling of the RX silicon is recommended. In the past, this was done in an oscilloscope using built-in equalization support (including CTLE, DFE, or FFE) and matching settings to the silicon implementation. However, when characterizing a system, a more accurate approach may be required.

For many years, silicon chip manufacturers have been trying to find a way to provide customers with information about their equalization implementations for system characterization, avoiding the need for dedicated simulation tools. As a standard solution, IBIS-AMI allows silicon chip manufacturers to build models of their silicon chips and make them available in non-dedicated simulation environments.

IBIS-AMI models can be used with either impulse responses or time domain waveforms. The time domain waveform approach is used in situations where an oscilloscope is used to process the model. Most IBIS-AMI models require an integer number of samples per bit. Because the number of samples per bit depends on the sampling rate of the oscilloscope and the bit rate of the input data signal, an integer number of samples per bit of the acquired waveform cannot always be guaranteed. To address this issue, the waveform can be resampled to support 8, 16, 32, 64, or 128 samples per bit. The configuration of the IBIS-AMI model is shown in Figure 6.

Figure 6: This screen is used to configure the IBIS-AMI model for RX equalization characterization using an oscilloscope.

The example below shows a 6Gb/s signal captured across a backplane. The eye diagram of the captured signal is completely closed (as shown in the eye diagram on the left in Figure 7). At this test point, one option is to use the built-in equalization support. For example, if the silicon implements a 3-tap DFE, the DFE can be specified in the link analysis software using the built-in DFE feature. However, an IBIS-AMI model can also be used, which more closely matches the silicon implementation. The signal after applying the AMI model is shown in the eye diagram on the right.

Figure 7: As shown on the left, the eye diagram of the acquired signal is completely closed. The right shows the result after applying the IBIS-AMI RX equalization model, which more closely matches the silicon implementation. [page]

Link Analysis Technology for DDR

Link analysis has traditionally been targeted at high-speed serial applications; however, techniques used in serial links have also been successful in other areas, including DDR memory. Typically, DDR signals are accessed using high-impedance probes, which can cause reflections on the acquired waveform. Link analysis software can be used to simulate probing different test points and eliminate reflections caused by measurement circuits and poor signal access points.

A typical scenario is shown in Figure 8. The acquired waveform has severe reflections caused by the impedance mismatch between the transmission line and the receiver input. Without any post-processing of the acquired waveform, it is impossible to analyze the signal.

Figure 8: Analysis of this DDR signal is impossible due to the impedance mismatch between the transmission line and the receiver.

As mentioned before, in order to de-embed reflections, the transmitter, channel, and receiver models must be known. However, in reality, it is often difficult to obtain models for all link elements. In the above case, an approximation can be used to compensate for reflections on the acquired signal. The transmission line delay and receiver load impedance can be estimated by performing simple timing and voltage measurements. By using cursors, the reflected/incident voltage ratio can be calculated as follows:

In the waveform shown in Figure 7, V2 = 1.2V and V1 = 0.75V. Therefore, we can estimate the RX input impedance to be approximately 200Ω. The next step is to estimate the transmission line delay from the actual probe location to the desired measurement point. By using the cursor, the round-trip reflection time is 660ps (as shown in Figure 9). To determine the time between the probe point and the desired test point, we divide this value by 2.

Figure 9: A DDR signal with markers can be used to measure the round-trip reflection delay to approximate the transmission line delay between the actual probe location and the RX input.

Using the link analysis tool, we can estimate that the test point is approximately at the input of the receiver. This is done by specifying the transmission line delay, the package model of the receiver, and the input impedance of the receiver. In this case, the package model of the receiver is defined by a 4-port S-parameter model. If the exact model of the transmitter, receiver, and transmission line is known, the final result (shown in Figure 10) will be more accurate. However, based on using the above techniques, the results are accurate enough to analyze the signal, including measurements and protocol decoding.

Figure 10: After removing reflections using the Serial Data Link Analysis tool and performing a probing simulation at the RX input, the DDR signal can now be analyzed.

Figure 11 shows a time domain impulse response representation of each of the above S parameter vectors. This is also a useful view because it easily shows the delay of the transmission terms. It also shows if the data was created within that time interval, because otherwise the validity of the S parameter set cannot be guaranteed. These curves are obtained by calculating the IFFT (Inverse Fast Fourier Transform) of the frequency domain S parameter data. This often requires extrapolating the frequency domain data to DC, and sometimes to the higher ideal Nyquist frequency.

Figure 11: The time domain plot of the 4-port S-parameter set for the data link is also a useful view because it easily shows the delay of the transmission line.

Conclusion

As signal transmission speeds increase and geometries shrink, powerful serial data link analysis becomes increasingly important. By using S-parameters, transmission line, or RLC models to create waveform transfer functions at each test point, such applications can update the live simulated test point waveform on the oscilloscope display. Various functions can be performed on the test points of interest, including protocol decoding, jitter and eye diagram analysis, or math functions. This is achieved directly using the link analysis software on the real-time oscilloscope. As described in this article, link analysis can achieve various goals, including de-embedding measurement circuits to measure the DUT at the TX pin location, applying silicon-specific equalization to open the eye, and eliminating reflections caused by non-ideal actual probing locations.