Design of portable infrared thermal imager based on 0MAP

Infrared thermal imagers use infrared detectors, optical imaging lenses and optomechanical scanning systems (the current advanced focal plane technology eliminates the optomechanical scanning system) to receive the infrared radiation energy distribution pattern of the target to be measured and reflect it on the photosensitive element of the infrared detector. Between the optical system and the infrared detector, there is an optomechanical scanning mechanism (the focal plane thermal imager does not have this mechanism) to scan the infrared thermal image of the object to be measured and focus on the unit or spectroscopic detector. The detector converts the infrared radiation energy into an electrical signal, which is amplified and converted into a standard video signal, and the infrared thermal image is displayed on a TV screen or monitor. This thermal image corresponds to the heat distribution field on the surface of the object. In addition to displaying infrared thermal radiation images, infrared thermal imagers can also provide accurate non-contact temperature measurement functions.

From the first generation of thermal imagers with scanning devices to focal plane array-structured condensation infrared thermal imagers, infrared thermal imagers have evolved from being bulky and complex to being lightweight, easy-to-use and portable handheld devices.

The continuous development of high-performance processor chips has brought new impetus to infrared thermal imagers. Using the right processor can improve the image processing speed and design more sophisticated products. This article discusses the design of an infrared thermal imager based on an uncooled focal plane detector and a high-performance dual-core processor OMAPl510.

1 Hardware Architecture

Since the infrared radiation thermal image distribution signal of the target object is very weak, it lacks layers and three-dimensionality compared with the visible light image. Therefore, in order to more effectively judge the infrared thermal distribution field of the target object in the actual detection process, some auxiliary measures are often used to increase the practical functions of the instrument, such as image brightness/contrast control, real mark correction, pseudo-color contour drawing, direct mathematical operations, printing, etc.

The portable infrared thermal imager is mainly composed of an infrared camera with a 320×240 uncooled focal plane detector, a preprocessing unit, an OMAPl510 processor and its peripheral devices, as shown in Figure 1.

The 320×2AO image data collected by the infrared camera is large in volume. After sampling, the electrical signal converted from the detector first passes through the preprocessing module, and the data is converted into 16-bit data and handed over to OMAPl510 for processing. OMAPl510 needs to process the image data by window position and width, 256-color pseudo-color conversion, brightness and contrast adjustment, etc., and finally display it on a 320×240 LCD screen.

OMAPl510 processor is a high-performance single-chip dual-core processor produced by TI. It mainly consists of TMS320C55 x DSP core, low-power enhanced ARM925T microprocessor, traffic controller, powerful DMA controller and rich peripherals.

TI's enhanced ARM925T core uses the ARM RISC architecture and operates at a main frequency of 175MHz. It includes a memory management unit, a 16KB high-speed instruction cache, an 8KB data cache, and a 17-word write buffer. There is 1.5MB of internal SRAM on the chip, which provides a large amount of data and code storage space for applications such as LCD displays. It has 13 internal interrupts and 19 external interrupts, using two-level interrupt management. In addition, there are ARM CPl5 coprocessors and protection modules in the core.

The C55x DSP core has the best power consumption performance ratio and operates at a main frequency of 200MHz. It adds three hardware accelerators: discrete cosine transform, inverse discrete cosine transform accelerator, motion estimation operation accelerator and half-pixel interpolation accelerator. The C55x DSP core has 32K words of dual-access SRAM, 48K words of single-access SRAM and 12K words of high-speed instruction cache. In addition, the core also contains a memory management unit (MMU), a two-level interrupt manager and a direct memory access (DMA) controller. [page]

The traffic controller is the hub for data exchange between the ARM925T processor and each memory chip, and also controls the access of the DSP, DMA controller and local bus interface to each memory. According to the characteristics of the off-chip memory, the traffic controller can flexibly configure the access word width, cycle and burst access of the whole word access.

The OMAPl510 chip has rich peripheral interfaces, such as LCD controller, memory interface, camera interface, Bluetooth interface, universal asynchronous receiver and transmitter, I2C host interface, pulse width audio generator, serial interface, host and client USB port, secure digital multimedia card controller (SD/MMC) interface, keyboard interface, etc.

2 Software Architecture

The software architecture is shown in Figure 2. The embedded Linux operating system is loaded on the MPU side to realize the reading of front-end image data, access to devices such as LCD, touch screen, keyboard, SD card, communication with DSP, and the running of Qt applications. The application's access to peripheral devices such as LCD is implemented by the corresponding Linux driver. The MPU also treats the DSP as a device and loads the so-called DSP driver on the MPU. The DSP side constructs data processing tasks based on DSP/BIOS to perform calculations on image data, such as window position and width adjustment, pseudo color color checking, brightness and contrast adjustment, etc. There are three ways to implement communication between the MPU and DSP: mailbox register, MPU interface and shared memory.

(1)MPU/DSP mailbox register

The MPU and DSP processor communicate through the mailbox interrupt mechanism. There are 4 mailbox register devices shared by the two cores in the public TIPB space. Among them, 2 mailbox registers are used for the MPU to send messages and send interrupt signals to the DSP, and the other 2 are used for the DSP to send messages and send interrupt request signals to the MPU. Each mailbox register device consists of 2 16-bit registers and a 1-bit flag register. The processor that sends the interrupt can use a 16-bit register to send a byte of data to the processor that receives the interrupt, and use another 16-bit register to send a word of command.

When one processor writes the appropriate command word to the command register and generates an interrupt to the other processor, setting the appropriate flag register, communication is achieved. The processor receiving the interrupt acknowledges the interrupt by reading the command word and clearing the flag register. At this point, the data register in each mailbox register is valid and can transmit 2 words of data.

(2)MPU Interface(MPU)

MPUI allows the MPU and system DMA controller to communicate with the DSP and its peripherals. MPUI allows access to all DSP memory spaces (16MB) and public peripheral buses. Therefore, the MPU and system DMA controller have read and write access to the complete DSP I/O space (128KB), including the DSP's public peripheral control registers.

(3)MPU/DSP shared memory

OMAP1510 implements a shared memory structure through the Traffic Controller. Therefore, both the MPU and the DSP can access the same shared memory SRAM (192KB) and EMIFF and EMIFS memory spaces. The MPU uses the DSP's memory management unit. The MMU determines which area of ​​the DSP is the shared memory that can be accessed. By allocating the shared memory area and defining the protocol for accessing this shared memory between the MPU and the DSP, the communication mechanism between the processors can be realized.

The communication between the MPU and DSP in this system is realized by combining mailbox registers and shared memory. Since the image data is large, and the mailbox register can only send 2×16 bits of data each time, it is not possible to efficiently share large amounts of data using only the mailbox. Although shared memory allows the MPU and DSP to share a section of memory, it lacks a synchronization mechanism. Using mailbox registers to establish a handshake signal (interrupt) allows the MPU and DSP to access the shared memory synchronously. After the MPU writes the original data to the shared memory, it sends a message by writing to the mailbox and sends an interrupt signal to the DSP to notify the DSP to process the data; and when the DSP finishes processing the data, it also sends a message by writing to the mailbox register and sends an interrupt signal to the MPU to notify the MPU that the data is ready.

During the test, it was found that there would be a delay when the MPU and DSP communicated through the mailbox. When the amount of data and the amount of calculation were small, the efficiency of the dual-core mechanism was low; when the amount of data and the amount of calculation were large, the dual-core mechanism was much more efficient than using only the MPU. The delay between the MPU and DSP communication has little impact on the entire system. When this system dynamically displays 320×240, 16-bit image data, the DSP performs window position and width processing, pseudo-color table lookup, and converts the data into a 5-6-5 format that the LCD can receive, with a display rate of about 18 frames per second. When these operations are handled by the MPU, the display rate is only 11.5 frames per second. [page]

3 Qt Application Design

There are several GUIs for embedded systems, such as MiniGUI, OpenGUI, MicomWindows, and Ot/Embedded. This system uses Qt/Embedded.

Qt is a multi-platform C++ graphical user interface toolkit developed by Troll Tech in Norway. It uses C++ language and has the characteristics of object-oriented programming, so programs written in Qt are easy to understand and maintain.

Qt/Embedded is an independent C++ graphical user interface application platform development tool based on the Linux embedded platform with frame-buffer support. It contains a complete set of GUI classes, operating system encapsulation, data structure classes, utilities and comprehensive classes, which can directly write to the framebuffer to avoid users using complex Xlib/Xserver systems. It provides all source code to embedded users and allows modification and further debugging. During the porting process of Qt/embedded, when the device used (such as touch screen, keyboard) is not a standard control supported by Qt, the Qt/embedded source code needs to be modified to enable the Qt program to respond to the device.

The software flow of the image display part of the Qt application of this system is shown in Figure 3. Its user interface has a window style. Selecting different options from the main menu will pop up the corresponding function window: full screen display of infrared thermal image; playback of images saved on the memory card (BMP bitmap); deletion of images on the memory card, temperature display of points of interest, etc. Click the exit button on the window to close the corresponding function window. The operation process can be completed by pressing keys or by clicking the touch screen. The entire GUI interface style is simple and easy to operate.

This paper explains the principle of uncooled infrared detection thermal imager through the development and design process of portable infrared thermal imager, and discusses the implementation method of OMAPl510 handheld terminal. The performance indicators of the infrared thermal imager designed in this way have reached a high level, such as high-speed dynamic camera of infrared thermal image, image storage to SD card, image playback, USB port image transmission and other functions. Practice shows that the dual-core structure of OMAP series is an embedded system chip with strong processing power, low power consumption and compact structure. It will show excellent characteristics in portable devices that require strong processing power.