Design of automatic tester for digital circuit boards of electronic equipment

1 Introduction

Electronic equipment is widely used in naval vessels, such as observation, navigation, command and control, electronic warfare and weapon control, etc., and is a key equipment of ships. With its intelligent, miniaturized, high-speed and high-complexity characteristics, electronic equipment has greatly improved the vitality and combat effectiveness of ships, but also brought huge challenges to ship maintenance and support departments and personnel. With the continuous popularization and deepening of the information construction of the army, the maintenance and support technology of weapons and equipment is undergoing new changes. Introduction: Automatic test systems and equipment ATE (Automatic Test Equipment), portable maintenance aids PMA (Portable Maintenance Aids), interactive electronic technical manuals IETM (Interactive Electronic Technical Manual) have become research hotspots in the field of weapon equipment maintenance. ATE is a computer-based fault diagnosis technology equipment. After being put into use, it accelerates the test process, improves the maintenance speed, and can also prevent unoccurred faults, thereby improving the quality and performance of equipment. There are many types of circuit boards in ship electronic equipment. Here we only consider the design of ATE equipment for simple digital logic circuit boards.

2 Overall system design

To test a simple digital logic circuit board, you first need to find out the signal characteristics on the circuit board interface pins, such as signal level (TTL, CMOS, etc.), signal direction (input, output or bidirectional), and signal function (power signal, logic signal). On this basis, analyze the circuit board function through the circuit schematic diagram and design test vectors to determine the response vector. There are the following ways to obtain signal characteristics and circuit schematics: (1) provided by the circuit board development and design unit; (2) manually measured using measuring instruments.

The principle of ATE testing is to input a test vector into the circuit board, obtain the corresponding output vector, and compare the output vector with the normal response vector. If the results are consistent, it means that the circuit board is fault-free, otherwise it means that the circuit board is damaged. The entire process is completed automatically by ATE, so it is highly efficient, but the completeness of the test vector has an important impact on the fault diagnosis results. The ATE device was developed for a certain electronic equipment system, and its structural block diagram is shown in Figure 1.

As shown in Figure 1, ATE consists of four modules: signal generation, signal acquisition, USB communication with the host computer, and connectors for connecting to the board under test. The signal generation module and signal acquisition module are implemented using the AT89S51+FPGA technology solution, so the entire test system is a four-level structure of PC → MCU → FPGA → board under test. The USB communication module is implemented using a USB/RS-232 converter, and the AT89S51 serial port is converted to an RS-232 interface through a level conversion circuit and then connected to the USB/RS-232 converter. The connector module mainly considers the electrical and mechanical characteristics of the connection with the board under test.

3 Key module design

3.1 Signal generation module design

The module consists of a single-chip microcomputer control bridge (AT89S51), a test vector memory (static memory HM628128x2, arranged in 256 Kx8 bit), a signal generation FPGA (Altera's Cyclone series PLD device EP1C3), a channel control CPLD (Altera's MAX7000 series PLD device EPM7128S) and a three-state gate array (74LS126x16). The module composition structure is shown in Figure 2.

After receiving the test vector from the host PC, the microcontroller control bridge writes it into the test vector memory (the memory in the microcontroller is not enough), and writes the pin signal characteristic data of the circuit board under test into the channel control CPLD. The CPLD controls the strobe end of the three-state gate array, and the input data of the three-state gate array is provided by the signal generator FP-GA. After receiving the signal generation command from the control bridge, the FPGA takes out the test vector from the test vector memory and sends it to the three-state gate array. The control bridge reuses the bus of the FPGA to access the test vector memory. In order to prevent the two from accessing the memory in conflict, the signals Ctrl0 and Ctrl1 are used for switch control. When Ctrl0=0 and Ctrl1=0, the control bridge controls the access bus of the memory, otherwise it is controlled by the FPGA.

One of the key issues to be solved here is the automatic wiring problem. Since the input and output pins of each circuit board are not fixed, in addition to ensuring that the signal is delivered to the corresponding input channel of the board under test, the automatic wiring needs to prevent the signal generation module from outputting the signal to the output channel of the board under test to prevent damage to the board under test. This problem is solved in the design through the high impedance state of the tri-state gate.

Since the board under test is a pure digital logic circuit, the output signal of the circuit board is a digital signal. Therefore, there is no need for A/D conversion when collecting signals. It is only necessary to collect the output signal according to a certain sampling period. Since the bit width of the microcontroller data input port is generally only 8 bits, in order to ensure the sampling speed, the inherent parallelism of the FPGA device is used to quickly collect the output signal and store it in the memory. After reaching the test depth, the FPGA sends an interrupt request to the microcontroller, and the microcontroller reads the collected output signal from the memory and transmits it to the host PC via USB. The module structure is shown in Figure 3.

Similar to the signal generation module, the MCU control bridge reuses the bus of the FPGA to access the output vector memory. In order to avoid bus access conflicts, the control bridge uses control signals Ctrl0 and Ctrl1. When Ctrl0=0, Ctrl1=0, the control bridge controls the bus to access the memory, otherwise the FPGA controls the bus.

4 System Working Principle

4.1 System working process

The basic principle of ATE testing is to input the test signal to the board under test, then obtain the output signal of the board under test and compare it with the response signal. Based on whether the two are completely consistent, it is determined whether the board under test has any faults. The ATE working process is as follows:

(1) Complete the hardware connection: USB connection between PC and ATE, plug the board under test into ATE, and connect the power supply;

(2) Run the ATE test control software TCS (Test Control Software) on the host PC. The model of each board to be tested has been pre-entered in TCS. The maintenance personnel selects the circuit board model and clicks the start test button;

(3) TCS reads the test data and parameters such as the pin signal characteristics, test vectors, response vectors, trigger words, trigger modes, sampling periods, sampling depths, and signal generation periods of the circuit board model from the database, and sends the data and parameters except the response vectors to the single-chip microcomputer AT89S51 in the signal generation module and the single-chip microcomputer AT89S51 in the signal acquisition module respectively;

(4) The AT89S51 microcontroller completes the system's automatic wiring by configuring the FPGA;

(5) TCS sends a start test command to the microcontrollers of the signal acquisition module and the signal generation module in sequence;

(6) After receiving the input and output vectors of the digital logic circuit board from the signal acquisition module, TCS displays the collected data in waveform form and compares the output vector with the response vector read from the database. Based on whether the two are consistent, it draws a diagnostic result on whether the digital logic circuit board under test is intact.

Items (3) to (6) above are automatically completed by ATE.

4.2 Test Vector and Response Vector Design

The correctness of the test diagnosis results is also related to the completeness of the test vector. The test vector can be obtained in two ways:

(1) Vector space complete set method: Assume that the number of circuit board input pins is n, then there are 2n signal combinations of n signal lines, that is, the test vector space is the set {0, 1, 2, ... 2n-1}, and all elements of this set are taken as test input vectors. This method can be completed automatically by a machine.

(2) Manual method: Analyze the logic function of the circuit board manually. Design the test input vector based on the principle that the various states of each logic gate, trigger and other devices can be fully traversed. For the sequential logic circuit board, the reset vector of the reset storage function device must also be determined, thereby obtaining the test input vector of the entire circuit board.

The scale of the test vectors obtained by manual method is much smaller than that of the complete set of vector space, which is conducive to saving time and storage space. In addition, the test vectors designed by manual method are more likely to reflect the functional characteristics of the circuit board for the sequential logic circuit. Therefore, all the test vectors of the digital logic circuit board of the electronic equipment system are analyzed and designed by manual method.

There are also two ways to determine the response vector required for the test result: (1) The response vector is obtained and saved by ATE testing the fault-free board as a benchmark for comparison during testing and maintenance. This method can be completed automatically by the machine; (2) Based on manual analysis, the response vector corresponding to the test input vector is determined. This response vector also needs to be manually compared with the circuit board output vector obtained by ATE testing the fault-free circuit board. Only when the two are consistent can it be determined that the response vector is correct and usable.

4.3 Design of automatic comparison of test results

In order to realize the automatic comparison between the output vector and the response vector obtained by ATE test, a virtual signal BASE is introduced into the test vector. This signal jumps between each step of the test vector and is sent to the idle 64th signal port on the ATE. The collected response vector (fault-free board) and output vector (tested board) contain the BASE signal, which becomes the step pointer. The time between the two signal jumps becomes a window, which represents a step in the test step. The response vector and the output vector are intercepted by this window respectively, and then compared to realize automatic software diagnosis. This automatic diagnosis method can handle the situation of monostable in a single step. At this point, the entire test process is fully automated, and the fault detection of a single digital circuit board can be completed within 1 minute. The operation is simple and the work efficiency is high.

5 Conclusion

The ATE designed for the digital logic circuit board of a certain electronic equipment system can complete the fault test of all digital circuit boards in the system. The test process is completed automatically, which is efficient and economical. It can meet the task of rapid maintenance of digital circuit boards in the electronic equipment system in wartime. It is easy to operate and has good practical application effect. The ATE can be further improved in the following aspects: (1) The plug-in module can be modified to use the ATE for the maintenance of digital logic circuit boards of other electronic equipment systems on the ship. This is the focus of the next step, that is, to improve the ATE from a dedicated digital circuit board maintenance automatic test equipment for a certain electronic equipment system to a universal ATE for digital logic circuit boards of all electronic equipment systems on the ship; (2) The ATE can currently only be used for fault testing of relatively low-speed digital circuit boards (below 20 MHz), which needs further improvement; (3) On the basis of the above, it can be considered to be improved and developed into a universal ATE for digital logic circuit boards of electronic equipment systems on the main ships in service of the Chinese Navy.