Studying RF interference on UART communication ports

Customers have reported that RF interference centered around 840MHz affects a serial communications port configured as a UART, which is located between a modem containing an AD6903 (LeMans LCR+) digital baseband processor and a host processor.

The problem is that noise appears in the UARTRX signal connected to the AD6903 GPIO_1 pin, and the signal average voltage moves away from its expected value whenever a radio frequency (RF) interference source is present. The magnitude of the deviation in the average voltage depends on the power and frequency of the RF source.

Figure 2 shows how the UARTRX signal entering the GPIO_1 pin of the AD6903 is affected when the RF power amplifier is turned on. In Figure 2, UARTRX entering the AD6903 is shown in pink, the UARTTX signal from the host processor is shown in purple, the power amplifier enable is shown in yellow, and the AD6903 VEXT supply is shown in green.

Figure 2: RF interference on the UART communication port.

When the power amplifier is turned on (yellow), the UART data transmission from the host processor's TX pin to the AD6903's RX pin (pink) fails because the RX signal rises to the middle between its high and low levels, which is inconsistent with the TX signal (purple). During the second pulse, when the power amplifier is turned on, both the host processor's TX pin and the AD6903's RX pin should remain high; however, there is noise on the TX pin and the RX signal falls to the middle of its high and low levels. Also note that the noise on the VEXT supply voltage (green) increases and its value rises slightly when the power amplifier is turned on.

However, the problem must be unrelated to the power amplifier enable signal and the power amplifier of the same modem, because RF energy from other nearby phones or signal generators can also affect the UART RX signal entering the AD6903. Using a signal generator sweep to check the susceptibility to RF interference found that the worst area is about 840MHz, and it is better at high frequencies or lower.

The series resistor of this signal between the host processor and the AD6903 is used to reduce the logic high level from 3.3V to 2.8V. The nominal resistance of this resistor is 10kΩ. It can be replaced with a smaller resistor, including a 0Ω resistor, because reducing the resistance value can reduce noise, but this will not solve the problem unless it is replaced with a short line.

This problem is not unique to the AD6903. Chips from other manufacturers also have similar phenomena. For example, the SN74AVCA16425GR has the same problem on pin 37. Please refer to Figure 3 for its functional block diagram.

Figure 3: SN74AVCA16425GR functional block diagram.

Here 1DIR, 2DIR are high level, OE is low level, so the operation is from port A to port B, and pin 37 (1A7) will receive data from another chipset. This means it is an input type.

In the presence of RF interference nearby, that is, using a mobile phone to make a call near the test point (within 5 meters), the signal on pin 37 of the SN74AVCA16425GR is tested. Figure 4 shows that when the device is not powered (I/O state is unknown), its output is abnormal; while Figure 5 shows the abnormal output when the device is powered (input state).

Figure 4: Low level rises.

Interference principle

This "RF interference pickup" behavior of the UARTRX signal entering the AD6903 occurs centered on a specific RF frequency, and these signal traces are not completely shielded. This phenomenon can be explained: the printed wires of the motherboard pick up interference because there are parasitic inductance, parasitic resistance and parasitic capacitance on the wires, and the two ends of the wires are connected to high impedance; one side is a 10kΩ resistor and the other side is a CMOS input. The wires on the circuit board are like an antenna with a 1/4 wavelength response.

Figure 5: High level reduction.

In the customer module, when calculating the GPIO1 wire, the module is calculated as 30mm, while the motherboard is about 15mm. So it is not surprising that this line can pick up RF noise and be sensitive to 840MHz. Please refer to Figure 6 for details.

Figure 6: RF interference calculation formula.

According to the above theory, it is recommended to add a capacitor to the signal path to damp the RF interference oscillation. The role of the capacitor is to change the tuning frequency of the antenna and reduce the antenna impedance, thereby reducing the antenna gain. Later, we heard reports that by selecting appropriate capacitance, the noise was reduced to an acceptable level.

The DC offset of this signal can be generated by the diodes of any CMOS input-output pin. They are usually called ESD (electrostatic discharge) protection diodes, but when it is configured as an output, they are actually used to control the depletion region of the transistor of the pin; those transistors often do dual purposes, that is, they also serve as ESD protection devices on the pin when configured as an input. So they are indispensable in all CMOS input/output circuit structures. These diodes are forward biased, and when the amplitude of the signal causes the diode voltage drop (about 0.6V) to exceed VEXT in the forward direction, or to be lower than the ground level in the reverse direction, the signal will be clamped. In order to increase the amplitude of the signal with the growth of RF energy in the antenna band, the average voltage of the signal will be close to half of the VEXT voltage.

This explanation tells us that the peak-to-peak value of the signal is from VEXT+0.6V to -0.6V. However, the amplitude measured by the oscilloscope is much smaller. To explain why the amplitude is reduced, we estimate that this is due to the attenuation caused by the oscilloscope probe and contact resistance, or the sampling rate of the digital oscilloscope is not enough. For example, in order to collect a complete signal near 1GHz (especially when the display window is about 10ms), the actual sampling rate may be much slower than the required 2G samples/second. This theory is described in Figure 7.

Figure 7: Explanation for DC voltage offset observation.

The RF interference signal is picked up by the printed wire and fed into the chip. The standard chip input/output attenuator acts as a rectifier. As part of all CMOS input-output pins (chip input/output), the diode is forward biased and clamps the signal swing when the forward voltage exceeds the diode drop (about 0.6V) above VEXT, or when the reverse voltage drops below ground. At the same time, the oscilloscope and/or probe cannot measure frequencies in the GHz range, and its performance is equivalent to a low-pass filter. Therefore, abnormal voltages appear at "some" I/O pins (depending on the printed wires connected to the I/O pins and the level of EMC design).

There are also reports that replacing the 10kΩ series resistor with a 0Ω resistor does not eliminate the interference or the DC level offset, but replacing it with a short wire can achieve this. Paying attention to those resistors can be explained. Even with a 0Ω resistor, there will be parasitic inductance due to the package in series with a certain amount of resistance. When considering high frequencies, this series RL component acts more like a low-pass filter than a pure resistor. Therefore, it seems that within the RF band where interference occurs, the resistance component may still have considerable impedance.

Solution The

above effects can be reduced/eliminated in two ways:

1. Eliminate/reduce the "interference source" and increase the system interference immunity (EMC protection) capability, such as isolating the RF circuit from other digital circuits, adding independent RF and baseband shielding areas, maintaining good grounding, and using EMC materials in the mobile phone housing.

2. In order to remove this "interference", a small capacitor should usually be used (note that the capacitor should be close to the I/O pin). By adding a 27pf capacitor to ground near the (AD6903.GPIO1) (UART_Rx) test point. From the oscilloscope measurement, it can be found that the input/output DC offset is eliminated. And the corresponding bit error rate of the UART communication port is normal. Refer to Figures 8 and 9 for details.

Figure 8: Low-level normal trace.

Figure 9: High level normal trace.