How to Successfully Complete ASIC Prototyping

There are many reasons why we do prototype verification before chip TAPOUT. The ultimate goal is to bring the chip to market as soon as possible with the highest cost-effectiveness. Prototype verification allows us to find errors that other verification methods cannot find. Because the speed of the prototype is close to the actual speed, prototype verification allows us to test the application software as early as possible. With the emergence of large-capacity FPGAs, it is cheaper and faster to build a cost-effective prototype verification system than other methods.

Prototype verification---Use software methods to discover hardware problems

Before the chip tap-out, the risks are usually calculated, such as the possibility of some serious errors. Usually someone is required to sign to confirm whether to go into production. This is a difficult decision. The NRE costs of ASIC products continue to rise. A failed ASIC tape-out will delay the time to market for several months. Who is willing to take the responsibility of signing? Some bugs cannot be caught through simulation and emulation. Traditional verification methods believe that the design function is correct if it meets the functional definition. But is the functional definition correct? The only way is to build a real hardware: a prototype.

FPGA-based prototype - a virtual reality environment

The similarity of density, speed, and other aspects to ASICs makes FPGAs a good choice for prototyping. The biggest concern is that the design process will be extended rather than accelerated. This is because setting up a prototyping system takes time, additional resources, and knowledge of FPGA design. Because the design capacity of FPGAs is smaller than that of ASICs, the design is usually divided into several FPGAs. The most difficult part is deciding how many FPGAs to use and how to plan the interconnections between them. During the planning process, the partitioning scheme is generally revised many times. Modules are moved between FPGAs, and the interconnections between FPGAs are changed accordingly. Some modules such as IP and memory require additional hardware outside the FPGA. The prototyping system must be flexible enough to solve these and more problems.

Another issue is how to apply ASIC code to FPGA. Partitioning the design to multiple FPGAs requires changing the RTL code. Partitioning may also result in wide buses between FPGAs, which may result in insufficient interconnects between FPGAs. The different structures of ASIC and FPGA may cause serious design problems. IP blocks, DesignWare components, and other ASIC-style code such as gated clocks must be converted to FPGA. Synplicity's Certify solution can solve these problems. Certify helps designers implement ASIC RTL code on multiple FPGAs.

Layout considerations

After solving the problem of logical implementation, we must consider the problem of physical implementation. We must design one or several circuit boards, which is not a simple task. Designing the layout of a high-speed FPGA circuit board will bring many problems, which require very professional knowledge to solve. Many factors such as crosstalk, reflection, transmission loss, ground bounce noise, etc. will affect signal integrity. The design of high-speed PCB boards not only requires the characteristics of digital circuits, but also the influence of analog characteristics.

Choose an existing mature product or choose to do it yourself

When you need the most flexible, easy-to-use, and reusable prototyping system, do you design it yourself? If time and money are taken into account, the decision is obvious. To build a prototyping system, investing in existing mature products is a smart choice. HAPS is a high-speed modular circuit board system designed specifically for ASIC prototyping. It is a commercial product with configurable performance that can be used in almost all applications. With Synplicity's Certify, ASIC code can be directly synthesized and mapped to the HAPS FPGA without major changes.

Application Examples

Philips Semiconductor built a verification system using HAPS and Certify to verify their 2.5G/3G multimedia baseband processor. During verification, they found some serious RTL bugs that were not found during simulation. Prototype verification was also used for software verification. This design has 2 million ASIC gates in addition to memory. They used a HAPS motherboard with four Virtex-II 8000 (1517-pin package) FPGAs. The memory used an external SDRAM daughterboard. The biggest challenge came from partitioning and balancing the utilization of each FPGA. In the best partitioning solution, there were 3000 interconnect signals between the two FPGAs. Since the number of signals exceeded the number of FPGA I/Os, this caused some trouble. The solution was to use Certify Pin Multiplexing (CPM).

Mihai Munteanu, a development engineer in Zurich, Switzerland, who participated in this work, gave the following advice to those who are starting to prototype: Analyze the ASIC design, taking into account the capacity, interconnects, clocks, and memory needs. Check all the RTL code and try to synthesize it into an FPGA. Be aware that some features of the ASIC are difficult to implement in an FPGA. Try

Use the fewest number of FPGAs to simplify the process. Use an incremental approach, but be aware that some problems may not arise with a reduced design. Also, use the latest and greatest tools.