Sodar signal acquisition system based on ADSP-TS201S

In the sodar system, the transmitter sends out acoustic signals of different frequencies in a directional manner, and then receives echo signals at different distances. The frequency deviation in the echo can be used to determine the changes in wind speed and direction with height. The system's multi-channel sampling data volume is close to 500k×32b/s, and 1100 million instructions are required to be processed within one frame time (about 2.7s). Its large data volume and the requirement for real-time processing put forward high requirements for the design of the signal acquisition and processing system. The signal acquisition system based on the DSP ADSP-TS201S and ADC AD7864 of Analog Devices introduced in this article can meet these requirements.

System Design

1 System Functional Module Division

The acoustic radar signal acquisition system is mainly composed of four parts: signal acquisition, signal processing, power supply and clock, as shown in Figure 1. The signal acquisition module consists of CPLD and 4 ADCs, which are responsible for completing A/D conversion; the converted data is sent to the signal processing module, DSP ADSP-TS201S is responsible for data reception and processing, two 512k×32b SRAMs complete the storage task of multi-frame data; a dual-port RAM provides a convenient interface for ADSP-TS201S and other processor boards to exchange information, and Flash is used to store user applications. The power supply module provides the voltage required for normal operation of other modules. In the clock module, the 27MHz clock generated by the crystal oscillator is obtained by the frequency multiplier chip to obtain a 54MHz clock and enters the CPLD. On the one hand, it serves as the system clock SCLK of ADSP-TS201S, and on the other hand, it serves as the working clock signal AD_CLK of AD7864 after 12 division in the CPLD .

The reason why this system uses the ADSP-TS201S chip is because of its powerful processing capability, which can process a large amount of echo data in real time. It can achieve 4.8 billion multiplication and accumulation (MAC) operations per second and 3.6 billion floating-point operations (FLOP) per second at a core clock of 600MHz, with a processing capability 50% to 100% higher than similar processors. It has an internal integrated 24Mb memory. This large on-chip storage capacity combined with an internal bandwidth of up to 33.6Gb/s is the key to improving performance. Its external 64-bit data bus and 32-bit address bus clock can reach up to 125MHz.

Figure 1 Signal acquisition system circuit diagram

The acoustic radar system requires multi-channel simultaneous sampling. The high-speed multi-channel and simultaneous sampling characteristics of the AD7864 chip meet the system requirements and simplify the hardware design. Its conversion accuracy is 12 bits, the throughput can reach up to 520KSPS, the single-channel conversion time can reach up to 1.65μs, and the sampling/holding time is 0.35μs. In addition, its single power supply and low power consumption characteristics (down to 20μW) also meet the system requirements.

When the system is working, the back-end processor board first sends an interrupt signal to ADSP-TS201S, notifying TS201 to read the command word from the dual-port RAM. According to the command word, TS201 controls the front-end ADC through CPLD to collect data and reads data using DMA. The processed data is stored in the dual-port RAM. TS201 also notifies the back-end processor board to read and display the data through interrupts.

2 Hardware Circuit Design

In the design of the clock circuit, the power supply of the crystal oscillator and the frequency multiplier chip should be isolated from the power supply of this board by inductors or magnetic beads to prevent them from generating coupling interference to the system power supply. In order to suppress the current surge and low-frequency interference caused by voltage fluctuations, a 10μF tantalum capacitor should be added to the power pins of both. A small capacitor of 0.1μF for suppressing high-frequency interference is also indispensable and should be placed close to the pins. In addition, care should be taken not to route under the clock chip to prevent mutual coupling interference. A 33Ω matching resistor can be added to the output end of the frequency multiplier chip to reduce the output current and improve the quality of the clock waveform. In order to reduce EMI radiation and clock jitter, the use of vias should be minimized.

(a) Ring structure

(b) Star structure

The design of the bus at high frequencies also needs attention, especially when the bus load in the system is heavy. Improper design will limit the bus to work at low frequencies, or even fail to read data. Since any load change on the ring structure will affect the work of other loads, a star bus structure is used in this design, as shown in Figure 2. In the wiring process, the driving capacity of the DSP bus is taken into consideration, and the length of each signal line is strictly controlled to about 6 inches. Practice has proved that the above measures are necessary and correct.

ADSP-TS201S and AD7864 have very high requirements for power supply. For example, when S201 requires a 500MHz core clock, the accuracy of its four power supplies VDD, VDD_A, VDD_IO and VDD_DRAM is ±5%. Therefore, the TPS54350 with an output voltage accuracy of up to ±1% is used as the power supply chip in the system.

The power consumption of ADSP-TS201S can be calculated as follows. Taking 500MHz as an example, the current consumed by the VDD domain can reach 2.67A. From formula (1), plus the current of VDD_A, the maximum power consumption of the core is 2.99W.

From formula (2), we can get that the maximum power consumption on the VDD_IO domain is 580mW.

From formula (3), we can get that the maximum power consumption of the internal RAM is 600mW.

Based on the above data, it can be obtained from formula (4) that the total power consumption of ADSP-TS201S at 500MHz is 4.17W.

(4)
The power consumption of ADSP-TS201S is relatively large, so space should be left for heat sinks or fans during design. High-frequency noise in the power supply part will affect the operating speed of ADSP-TS201S, especially when the voltage is lower than 1.5V. Therefore, low-ESR ceramic chip capacitors should be used for filtering near the power input pins of TS201. In addition, the VREF and SCLK_VREF pins also need to be filtered.

Since the system is a mixed analog-digital circuit including ADC, the following issues should be noted in the design. A large area of ​​copper cladding near the AD7864 and CPLD can shield external interference to the analog signal. At the same time, a 0.1μF chip capacitor should be added between the power pin, reference voltage input pin, VDRIVE pin and analog ground of the AD7864 for decoupling; the digital signal routing and analog signal routing should be laid separately; the digital ground and analog ground of the entire board should be separated and connected at a single point, and the connection point should be selected where the analog and digital signals converge; the 5V power supply for the AD7864 needs to be far away from the AD7864.

During the debugging process, it was found that if a driver chip is not added to the JTAG port of ADSP-TS201S, Visual DSP will fail when entering the hardware simulation environment. Therefore, it is recommended that even a single-chip ADSP-TS201 system should add a driver chip, such as TI's 74ACT11244.

In order to improve the flexibility of the system, it is recommended to provide pull-up and pull-down options for the SCLKRAT0~2 (used to select the multiplication factor) and DS0~2 (used to select the bus drive capability) pins of ADSP-TS201S, respectively, and flexibly configure them according to the actual situation during debugging.

3 Software Implementation

The software design of the data acquisition system includes the software design of the CPLD and the program code inside the DSP. Some input pins of the AD7864 need to be configured, and the CPLD product MAX3256A from Altera completes this task. The specific status of each pin that needs to be configured on the AD7864 is shown in Table 1.

The data output control of AD7864 adopts the time-sharing output mode. The four AD7864s are divided into two groups: 1 and 2 pieces in one group, and 3 and 4 pieces in one group. The sampling signal comes from the timer/counter of TS201. Every time the timer counts full, the TMROE pin will generate a high level of 4 bus clocks (SCLK, 54MHz). This signal is inverted in the CPLD and used as the CONVST signal of AD7864. By delaying the CONVST signal of pieces 3 and 4, the two groups of AD7864 can be controlled to work in time-sharing mode. The delay circuit and simulation waveform are shown in Figure 3. By adjusting the values ​​of the two comparators, a waveform that meets the system requirements can be generated.

Figure 3 CONVST delay circuit and simulation waveform

In data transmission, the data of chips 1 and 3 occupy the low-order data line, and the data of chips 2 and 4 occupy the high-order data line. The time-sharing output prevents the occurrence of bus conflicts. Since AD7864-1 is a complement code output, the DSP needs to perform data extraction and sign extension after reading the data back. Data extraction mainly separates the high and low-order data, and sign extension is to judge the positive and negative of the data based on the 12th bit of the collected data and perform different high-order extensions. The specific procedures are as follows.
j0 = datum_out0;;
xr0 = [j0+=0];;//Read the AD converted data
xr1 = 0xfff;;
xr2 = r0 and r1;;//Extract the 12th bit of the AD converted data
xr3 = 0x800;;
xr4 = r2 and r3;;//Judge whether the sign bit is 1
if AEQ, jump data(np);;//If the sign bit is not 1, jump
xr5 = 0xfffff000;;//If the sign bit is 1, high bit extension
xr6 = r5 or r2;;
xr2 = xr6;;//xr2 contains the extended AD converted data
data:
......//Further data processing

Conclusion

After testing, the system bus works normally at 54MHz clock, data transmission is correct, and at the core clock 432MHz, the data processing and display tasks are successfully completed (the actual time consumed is about 2.55s for 1100M/432M, which is less than one frame time). At present, this design has been successfully applied to a certain acoustic radar signal acquisition system.