High-speed data transmission interface DDR2 I/F characteristics and testing

Preface

In recent years, with the development of video equipment and personal computers, the 3D processing, video exchange and complex calculations on these devices have led to a sharp increase in the amount of data. In order to meet the high-speed exchange of these data between processors, memory and peripheral devices, a variety of high-speed interfaces have emerged in recent years. At the same time, due to the high-speed data transmission, it also brings new technical and test cost challenges to testing. This article will briefly introduce the characteristics and testing of the recently emerged high-speed data transmission interface DDR2 I/F based on Advantest's T6500 series test system.

High-speed memory i/f overview

For a simple explanation, Table 1 lists the correspondence between PC memory bus, microprocessor, memory unit and high-speed interface from 1990 to the present. It can be seen from the table that the speed of the transmission bus has increased rapidly with the transition from SDR to DDR2. With the increasing amount of data, DDR2 memory has become the mainstream application of memory and graphics processing chips. Therefore, the application of DDR2 I/F in SOC chips is becoming more and more extensive.

DDR2 integrates a 4-bit pre-fetches transmission line between the memory cell and the I/O buffer. DDR1 of the same frequency only integrates 2 bits, so the data frequency of DDR2 can reach twice that of DDR1 (as shown in Figure 2).

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The pinout of DDR2 I/F is shown in Figure 3. The pins that determine the characteristics of DDR2 I/FI/O are DQS (data strobe signal) and DQ (data). CLK is used to provide an external clock signal, COMMAND is used to provide control instructions, and DM is used to mask the output of certain data bits.

Different from the traditional data transmission method, the input and output of DDR2 data is not synchronized with the external clock signal, but is controlled by the differential DQS (data strobe signal). As shown in Figure 4, the data output of DQ is triggered by the rising and falling edges of DQS. In this way, high-speed transmission of DDR2 chip data can be achieved.

DDR2 I/F test requirements

The data transmission frequency of DDR2 I/F is very high, and the quality requirement of the transmission signal is also relatively high. Advantest provides T6577+DDR2 I/F option module to meet various performance tests and low-cost test requirements of DDR2 I/F.

Taking DDR667 (data frequency 667 Mbps) as an example, the following briefly introduces the test conditions required on the corresponding signal pins when testing it and the corresponding test methods:

DQS/DQN test conditions: signal frequency: 667 Mbps interface specification: SSTL18
clock test conditions: signal frequency: 333 Mbps interface specification: SSTL18
Relationship between DQS and DQN: The DQS signal controls the continuous input and output of data on the DQN pin.
AC parameter test conditions: The option module provides high-frequency time parameter test conditions.
DC parameter test conditions: The built-in MDC and UDC measurement units of T6577 are used to perform high-precision tests on the DC parameters of DDR2 I/F.

T6577+ DDR2 I/F option module schematic diagram

667 Mbps/SSTL18 output signal: T6577 high-speed output mode can correspond to
333 MHz/SSTL18. Continuous clock signal supply: Option can provide low jitter signal.
Option is required to detect the output of DQ and DQS and the relationship between them: Using the source synchronous function and SDR function of option can correspond to
667 Mbps/SSTL18 input and output signal accuracy guarantee: Through dual transmission line and option, the signal reaches the accuracy requirement.
There is a certain delay between DQS and STRB signals in AC test: Through option, variable time delay can be provided, delay time ±1ns, resolution 20ps
DC test: T6577 DC test unit can correspond [page]

T6577 corresponding test method

The T6577+ DDR2 I/F option module can be used to test the signals on the DDR2 I/F DQ and DQS pins. Figures 6 and 7 show the test items that the T6577 can complete in different data input/output cycles and the test conditions provided to complete the DDR2 functional test.

in conclusion

From the above introduction, we can see that T6577 + DDR2 I/F option module can fully meet the high-speed and high-precision test requirements of high-speed DDR2 I/F, and realize low-cost DDR2 I/F test. As a general SOC test system, T6577 can meet the test requirements of various SOC, ASIC, RF/mixed chips, and complete high-speed and high-precision tests of various types of chips.