Design of micro storage system based on attitude measurement

Overview

Micro-attitude test systems play an increasingly important role in the field of aerospace science and technology, and have important reference significance for determining various flight attitudes of flying objects. In the field of testing, low power consumption, small size, low noise, and large capacity have become the main goals of competition. Micro-attitude test systems are mainly used for the measurement, collection, encoding, and recording of the three-dimensional angular velocity and linear acceleration parameters of flying objects from the time of their release to the time of their landing, and for the post-reading and processing of telemetry data after the hard recovery of the flying objects.

In the design of this paper, the flight body attitude micro memory test system has achieved and satisfied the high performance indicators and many technical requirements that are difficult to meet in the past. Among them, small size, low power consumption and high overload resistance are the main aspects of this design. The design requirements of small size and low power consumption are guaranteed from the aspects of system structure design, power supply design and state design, and the high overload resistance of the whole system is also improved.

1 Module composition and working principle of micro attitude storage and measurement system [1] As shown in Figure 1, it is a block diagram of the micro attitude storage and measurement system. The whole system consists of an overload switch, an inertial combination, a power supply control and conversion circuit, a signal conditioning circuit, an A/D conversion system, a central control logic unit, a FLASH memory and a reading interface circuit.

When the flying object reaches the rated overload during flight, the overload switch will trigger the start signal. The three-dimensional angular velocity and linear acceleration parameters of the flying object will be converted into analog signals for collection by the recorder by the inertial combination. The recorder will collect, frame and store the analog signals under the timing control of the FPGA central control unit. When the recorder is retrieved, the data in the memory will be read and processed afterwards by the ground detection system.

After receiving the "start" command, the power control and conversion module converts the power on the flying body to the inertial combination, and converts the system battery to output 3.3V to power the entire recording device. The signal conditioning module conditions the inertial combination signal into a 0-3.3V signal that can be received by the recording device, while ensuring that the recording device has sufficient input impedance, that is, it does not affect the electrical characteristics of the measured signal.

The function of the 6-channel 12-bit A/D conversion system is to collect the 6 signals sent by the inertial combination at a sampling rate of 12KHz under the control of the central control logic module, and send the collected data to the central control logic module.

The central control logic module is the core part of the whole recording device. Its function is to collect the data sent by the 6-channel 12-bit A/D conversion system in sequence and send it to the 128M 8-bit FLASH memory. Its sampling rate is 2KHz.

When the central control logic module starts working, it will send a "self-protection" command to the power control and conversion module to ensure that the power control and conversion module can still work normally even after the overload switch is disconnected, that is, to ensure the triggering validity of the overload switch. The 128M capacity 8-bit FLASH storage module is mainly used for data storage, with a capacity of 128M and a data bit of 8 bits. Since the FLASH memory has the function of retaining data when power is off, there is no need to design a backup battery to protect data when power is off. According to the previous technical indicators, the capacity of 128M far meets the required storage capacity.

The reading interface module is mainly used to read the data when recording the device is detected and after recovery. 2 Hardware Design of Micro Memory System The micro attitude memory test system has strict requirements on the power supply, because this test system is powered by a battery. According to the design principle of low power consumption, this design uses the MAX8882 low voltage difference power control chip, which can simultaneously convert 3.3V and 2.5V voltages for the input 3.5V~5V voltage. The power consumption of the entire system can be effectively controlled by controlling the power chip through the logic program. When the power control system is started, the logic control center generates a self-protection signal to control the shutdown enable terminal of MAX8882 to enable the normal power supply of the entire system. When the acquisition and storage process is completed, the logic control center generates a trigger signal to control MAX8882 to stop working, so that the entire system is in an energy-saving state.

The circuit design idea of ​​the micro attitude memory is mainly based on the real-time acquisition, framing and storage of the attitude parameters of the flying body. The signal conditioning circuit divides the attitude analog signal, filters it and transmits it to the analog-to-digital conversion chip after following the op amp. The analog-to-digital conversion circuit uses the MAX1295 chip of Maxim, which is a 6-channel 12-bit precision successive approximation digital-to-analog converter with a sampling rate of 265Ksps. It integrates a high-performance sampling and holding circuit and a reference voltage source. It also has low power consumption and high signal-to-noise ratio, and can be set for internal and external sampling modes. In this design, the external sampling mode is used.

The storage system uses Samsung's K9F1G08 FLASH memory. The chip has good performance and a small package, which provides convenience for the design of miniaturized test systems. Under the timing control of the logic center, the memory is read, written, and erased. Each operation uses the interrupt method of the FLASH status signal r/b. During the write operation, 8-bit data is accessed. When storing a page of data, page programming is required, which takes about 300us to 700us. After waiting for the change of the r/b status signal, the next page of storage is entered. In order to match the acquisition and storage speeds, 8K Bits dual-port RAM is used inside the FPGA. Data is cached when the FLASH memory is page-programmed. During the erase operation, the FLASH memory is block-erased. It takes 2ms to 3ms to erase a block. After waiting for the change of the r/b status signal, the next block is erased. Similarly, in the data read operation, each byte must wait for the r/b interrupt, and the data is transmitted to the host computer through the test bench and USB cable. [page]

Another major highlight of the micro-attitude memory test system designed this time is its miniaturization. All chips of the entire recorder are packaged in miniaturized surface mount packages, and the circuit board is made with a four-layer board process, with the power layer and the ground layer in the middle. This not only greatly reduces the size of the recorder, but also plays a certain positive role in signal isolation and anti-interference.

3. Logical Flowchart Design

The flow chart is shown in Figure 2. The whole process starts with the overload switch starting the power control chip to start the control timing of the entire FPGA. The reset module is composed of the host computer reset, power-on automatic reset and soft reset. When the whole system is started, the system must first be initialized and reset, and a trigger signal "esok" is defined to be initialized to "0" to trigger the control unit and put the system into the self-test state. In the self-test module, the FPGA must first read 16 pages of data from the sixth page of the FLASH memory and determine whether the data is "FF". If not, there is data in the memory and the system will stop in this state; if so, the trigger signal "esok" is "1" to start the A/D data acquisition module and the FLASH data storage module. At this time, the central control module responds to the interrupt of the acquisition module to make the A/D module write data to the dual-port RAM inside the FPGA at a sampling rate of 16K. At the same time, the FLASH storage module judges and advances the RAM address under the central control module to read the RAM data. While the data is continuously written to the FLASH memory, it determines whether the data capacity reaches the specified data volume. If not, Then it returns to the FLASH write state to continue storing data. Once it reaches the limit, the system triggers a signal to control the power module to turn off the power, so that the entire system stops working to reduce power consumption. When the reading port is plugged in, the USB is started online. Under the control of the host computer, the FLASH memory is read for subsequent analysis and processing of the data.

Conclusion

The micro-attitude storage test system has good working performance. In the scattering test, the signal shown in Figure 3 was obtained, which met the theoretical requirements and successfully completed the collection and storage of the flight body attitude parameters. Through multiple tests, it has been proved that the micro-test system has certain engineering applicability and has important reference significance for other test designs.