AI is actually very simple — A new era of financial technology (Fintech) development has arrived
In today's world where big data and artificial intelligence are prevalent, data in the field of financial technology (Fintech) is becoming increasingly dense and sensitive. Financial applications such as high-frequency trading and risk analysis have long been tepid, but Xilinx FPGA, which is in a high position but lonely, has ushered in an unprecedented market boom.
The reason why FPGA is popular in the Fintech field is that it has rich and flexible logic and computing units inside, which can support customized low-latency and high-throughput designs. On the one hand, it can provide Fintech with performance advantages that far exceed software implementation, and on the other hand, it can provide financial companies with flexible and adaptable cost advantages that can follow the latest technological evolution. However, the once high-end FPGA has also been criticized by some users for having a high "threshold" for use. In other words, when using FPGA products, developers must have both "soft and hard" skills, and they must know both software and hardware. Moreover, writing RTL code and verification are time-consuming and labor-intensive. In the financial industry where every second counts and time is money, developers have a love-hate relationship with FPGAs, just like the lyrics "It's not easy to say I love you, it takes too much courage"
Just when developers were struggling, two epoch-making "tools" from Xilinx came out, which reduced the difficulty of FPGA development from the top of the pyramid to the bottom of the pyramid, greatly reducing the difficulty for software and hardware programmers to develop FPGA applications: from then on, software and hardware programmers can develop FPGA applications easily, and no longer have to suffer the pain of allocating pins and handwriting RTL. So, what are these two tools? They are Xilinx Vivado HLS high-level synthesis tool and Alveo adaptive computing accelerator board. Why are they so magical? Please listen to me carefully.
one
High-level synthesis tool: Vivado HLS
Vivado HLS is an automatic conversion tool that can convert C/C++ code into RTL code, and it has built-in verification, packaging and other functions. Developers only need to match the top-level C/C++ program with C/C++ verification code, pass software verification, and then use Vivado HLS to convert it into RTL code. Secondly, Vivado HLS can use the original C/C++ verification code to co-generate RTL code, perform simulation and verify functional correctness. Finally, Vivado HLS supports one-click packaging and generation of IP for use in Vivado® tools or SDAccel development environment.
Figure 1: Vivado HLS tool algorithm flow
So simple? Where does the performance come from? That is the powerful performance of the Vivado HLS design suite: it can use the instruction pipeline (pipeline), task-level pipeline (dataflow) and operation unrolling (unroll) functions to enable all operations to run non-stop on the timeline, and all of this can be achieved by just clicking the mouse and inserting a few instructions (pragma).
Figure 2: Parallel processing in Vivado HLS
two
Adaptable Accelerator Cards: Alveo
Let's take a look at what the Alveo board can bring us and where it is powerful. Alveo is an adaptive accelerator card series launched by Xilinx to adapt to the new era of flexibility and intelligence. It is equipped with standard PCIE and network ports (up to 100G), and also provides a complete set of deployment and development software stacks, so that developers can easily deploy it by installing software packages. At the same time, Alveo is also equipped with a shell that can solidify functions such as PCIE and DMA. Developers only need to develop the most innovative and proprietary kernels and use the standard AXI-4 interface to automatically connect the kernel to the shell to generate a complete platform hardware. At the software level, developers only need to call Open CL or the API provided by Xilinx to complete all tasks such as board scheduling and data transmission.
Figure 3: Platform model and execution model of Alveo and SDAccel development environments
Alveo adaptive accelerator cards are applicable to a wide range of fields, such as databases, machine learning, image processing, compression and decompression, encryption and decryption, financial computing, etc. Alveo has excellent acceleration applications in each field. Although the acceleration multiple of Alveo varies depending on the application, it can often provide more amazing performance in some fields suitable for parallelization. For example, without losing accuracy, European option pricing can be more than 3,000 times faster than CPU. The figure below shows the application of Alveo in multiple fields of Xilinx and its partners.
Figure 4: Alveo acceleration example
Opening a new era of Fintech development
The software has the SDAccel development environment and scheduling library (runtime), the hardware has the Alveo adaptive accelerator card and shell, and the design has Vivado HLS to develop customized requirements. In addition to rich cases and open source practical applications, Xilinx has opened up a new era of FPGA acceleration development for developers in the financial technology field that is easy to get started with.
In addition, Xilinx also acquired Solarflare, a company well-known in global financial institutions, which greatly enhanced Xilinx's strength in the Fintech field and can provide customers with low-latency network cards and various customized applications in the financial field.
At the same time, Xilinx has also created a comprehensive Fintech ecosystem. The company not only provides developers with a series of tools, but also provides a variety of IPs. Even some special needs in the financial field, such as TOE (TCP/UDP Offload Engine), also have corresponding open source HLS to help implement. In the HLS basic library, it covers fixed-point library, mathematical function library, linear algebra library, etc. At a higher level, Xilinx has also realized HLS open source at the module level and software API level, such as matrix operation library.
Figure 5: Solarflare
In addition to providing a full set of tools and open source libraries, Xilinx also provides various solutions together with independent software providers (ISVs). These ISVs often have their own unique solutions, and what Xilinx has to do is to support their applications to meet the needs of many fields. In the field of Fintech, these applications include:
-
One-click order (Tic To Trade);
-
Trading rights risk control;
-
Unpacking and dispatching;
-
Option pricing, etc.
The fastest order placement can even be achieved in nanoseconds. In the Chinese market, from receiving the exchange package on Ethernet to unpacking and then completing the calculation, the entire process can be achieved in hundreds of nanoseconds.
Figure 6: SDAccel tool chain-level Fintech platform example
In short, with the arrival of Xilinx Vivado HLS and Alveo, Fintech development has ushered in a new era of FPGA acceleration. Developers do not need to invest too much energy in hardware platform construction and basic support tools, but only need to focus on their own areas of expertise, and use Vivado HLS to quickly implement customized applications on Alveo™ accelerator cards, constantly breaking through the limits of low latency and high throughput.
Finally, if you want to experience the above performance yourself, I strongly recommend Xilinx's current product: Binomial Option Pricing Model. It is simple to use and easy to get started, and can achieve up to 60.8 times acceleration compared to a 12-core CPU. You can click the link to experience it https://github.com/Xilinx/BinomialModel.
Figure 7: Binomial Option Pricing Model
Click " Read original text "
View more Xilinx Fintech solutions
-
FPGA Acceleration Derivatives Pricing Model - SciComp
-
RTR (Real Time Risk) - Maxeler
-
PTRC (Pre-Transaction Risk Detection System) - Algo-Logic
-
Xilinx Computation Library, Binomial Option Model - Xilinx
-
SIMM (Standard Initial Margin Model Calculation - Maxeler
-
High-performance Monte Carlo option pricing simulation
Xilinx official account
Creating a world where everything is smart and adaptable
Long press the QR code to follow us
京公网安备 11010802033920号