The next logical step in C/C++, OpenCL programming

Mike Santarini

Xilinx, Inc. Publisher of Xcell Publications

Lawrence Getman

Vice President of Corporate Strategy and Marketing, Xilinx

Since Xilinx developed and launched the world's first FPGA in the early 1980s, these versatile programmable logic devices have become the MacGyver of hardware engineers. Xilinx recently released the SDx™ family of development environments (i.e., SDAccel™, SDSoC™, and SDNet™), which enables software developers and system engineers (non-FPGA designers) to easily create their own customized software-defined hardware using Xilinx devices, thereby empowering more creative minds to realize extraordinary innovative technologies.

Before introducing these new environments and other software development resources provided by Xilinx and its alliance members, let's consider the evolution of processing architectures and their impact on software development.

Before 2000, the typical microprocessor consisted of a giant monolithic processor core with onboard memory and a few other components that made the MPU a relatively simple and intuitive platform for developing new generations of applications. For the three decades before that, microprocessor manufacturers had been introducing devices with higher capacity and performance every 22 months at the rate of Moore's Law. They would simply increase the clock rate to improve performance. The fastest monolithic MPU at the time was the Intel Pentium 4 Pro, which had a top speed of just over 4GHz. This evolution was important to developers because with each generation, their programs became more complex, performed more refined functions, and ran faster.

Figure 1: Zynq UltraScale+ MPSoC

But in the early 2000s, the semiconductor industry changed the game, forcing developers to adjust to a new set of rules. The shift began with the realization that if the MPU industry continued to increase clock rates in new monolithic MPU architectures, then given the chip process technology roadmap and worsening transistor leakage issues, MPUs would soon reach the same power density as the sun.

Because of this, the MPU industry is rapidly transitioning to a homogeneous multiprocessing architecture, in which computing tasks are distributed across multiple small cores running at lower clock rates. The new processing model allows MPU and semiconductor manufacturers to continue to produce new generations of higher-capacity devices and integrate more functions into a single chip for higher performance. However, existing programs cannot take advantage of the new distributed architecture, so software developers must find ways to develop programs that can run efficiently across multiple processor cores.

Meanwhile, subsequent generations of chip process technology continued to multiply transistor counts, allowing semiconductor companies to take another innovative step by integrating different types of cores onto the same chip to create SoCs. These heterogeneous multiprocessor architectures present additional challenges for embedded software developers, who must develop custom software stacks to enable applications to run optimally on the target system.

Today, the semiconductor industry is changing the rules of the game again, but this time software developers are welcoming the change. Faced with another power dilemma, semiconductor and system companies are turning to heterogeneous processing architectures accelerated by FPGAs. This architecture closely combines MPUs with FPGAs to improve system performance at a minimal power cost. The most notable application of this emerging architecture is in new data center processing architectures. In a now-famous paper, Microsoft researchers showed that combining MPUs with FPGAs in the architecture can achieve a 90% performance improvement while increasing power consumption by only 10%, far superior to the architecture achieved by combining MPUs with high-power GPUs in terms of performance per watt.

The benefits of heterogeneous multiprocessing architectures accelerated by FPGAs extend beyond data center applications. Embedded systems using Xilinx Zynq®-7000 All Programmable SoC devices benefit from the perfect integration of ARM processors and programmable logic on a single chip. Systems using the upcoming Zynq UltraScale+™ MPSoC are set to be even better. The Zynq UltraScale+ MPSoC integrates multiple ARM® cores (4 Cortex™-A53 application processors, 2 Cortex-R5 real-time processors, and 1 Mali™-400MP GPU), programmable logic, multiple levels of security, increased safety, and advanced power management blocks in a single device (see Figure 1).

However, to make these FPGA-accelerated heterogeneous architectures suitable for large-scale deployment and convenient for software developers to use, FPGA vendors must develop new environments. In this regard, Xilinx provides three development platforms: SDAccel for data center developers, SDSoC for embedded system developers, and SDNet for network line card architects and developers. These new Xilinx environments allow developers to easily put the slow parts of the code on the programmable logic to accelerate the program, thereby creating the best system.

The latest Xilinx SDAccel development environment provides a complete FPGA-based hardware and software solution for data center application developers (Figure 2). The SDAccel environment includes a fast, architecturally optimized compiler that can effectively utilize on-chip FPGA resources. The environment provides developers with a familiar working environment and software development flow similar to CPU/GPU, and has an Eclipse-based integrated design environment (IDE) for code development, characterization and debugging. Using this environment, developers can create dynamically reconfigurable accelerators that can be swapped in and out on the fly for different data center applications. Developers can use this environment to create many applications that can swap many cores in and out of the FPGA at run time without interfering with the interface connection between the server CPU and the FPGA, thereby achieving uninterrupted application acceleration. The SDAccel environment targets host systems based on x86 server processors and provides commercial off-the-shelf plug-in PCIe cards to add FPGA capabilities.

With the SDAccel environment, developers with no prior FPGA experience can use SDAccel's familiar workflow to optimize their applications and get the most out of FPGA platforms. The IDE provides coding templates and software libraries, and can be used to compile, debug, and profile all development targets, including simulation on x86, performance verification using fast simulation, and native execution on FPGA processors. The development environment executes applications on FPGA platforms for data centers and automatically inserts tools to achieve all development targets. Xilinx designed the SDAccel environment to enable CPU and GPU developers to easily migrate applications to FPGAs while maintaining and reusing OpenCL™, C, and C++ code in a familiar workflow.

Figure 2: The SDAccel development environment for OpenCL, C, and C++ delivers 25X better performance per watt for accelerating data center applications using FPGAs.

SDAccel libraries play a major role in enabling a CPU/GPU-like development experience for the SDAccel environment. The SDAccel libraries include low-level math libraries as well as higher productivity libraries such as BLAS, OpenCV, and DSP libraries. These libraries are written in C++ (not RTL) so developers can use them exactly as written during all stages of development and debugging. Early in the project, all development work is done on the CPU host. Because the SDAccel libraries are written in C++, they can be compiled along with the application code on the CPU target (creating a virtual prototype), allowing all testing, debugging, and initial characterization to be done on the host. No FPGA is required at this stage.

Xilinx designed the SDSoC development environment for embedded system developers to program Xilinx Zynq SoCs and the upcoming Zynq UltraScale+ MPSoC. The SDSoC environment provides a greatly simplified embedded C/C++ application programming experience, including an easy-to-use Eclipse IDE that can run on bare metal or operating systems such as Linux and FreeRTOS. The environment is a comprehensive and comprehensive development platform for heterogeneous Zynq SoC and Zynq MPSoC platform deployment (Figure 3). The SDSoC environment also comes with the industry's first C/C++ full-system optimizing compiler, supporting system-level characterization, automatic software acceleration in programmable logic, automatic system connection generation, and a variety of libraries that can speed programming. The environment also provides development flows for customers and third-party platform developers to enable platforms to be used in the SDSoC development environment.

Figure 3: The SDSoC development environment provides a familiar embedded C/C++ application development experience, including an easy-to-use Eclipse IDE and a comprehensive design environment for heterogeneous Zynq All Programmable SoC and MPSoC deployments.

SDSoC provides board support packages (BSPs) for Zynq All Programmable SoC development boards such as ZC702 and ZC706, as well as third-party and market-specific platforms including ZedBoard, MicroZed, ZYBO, and Video and Imaging Development Kits. The BSPs contain metadata that abstracts the platform from the code of software developers and system architects to simplify the creation, integration, and verification of intelligent heterogeneous systems.

SDNet is a software-defined specification environment that uses an intuitive, high-level, C-like language to design requirements and create network line card specifications (Figure 4). The environment enables network architects and developers to create “soft” defined networks that extend programmability and intelligence from the control plane to the data plane.

Traditional software-defined network architecture uses fixed data layer hardware and connects to the control layer through narrow southbound APIs, but soft-defined networks are different. They are based on a programmable data layer with content intelligence and a wide northbound API control layer connection. This enables a variety of breakthrough features, including: supporting independent line-speed services to avoid the complexity of various protocols; providing flexible services based on processes; supporting revolutionary innovative "lossless business" upgrades while running at 100% line rate.

Figure 4: The SDNet environment enables network architects to create specifications in a language similar to C. Once the hardware team completes the design, developers can use SDNet to upgrade or add protocols to line cards in the field.

These unique capabilities enable carriers and multi-service system operators (MSOs) to dynamically deliver differentiated services without any disruption to existing services, hardware qualification or truck rolls. The dynamic service delivery capabilities of the environment enable service providers to increase revenue and accelerate time to market while reducing capital and operating expenses. Network equipment vendors realize that they can also gain the same benefits through the SDNet platform, enabling them to achieve greater differentiation by deploying content-aware data layer hardware programmed by the SDNet environment.

To further help embedded software engineers with programming, Xilinx provides a full set of embedded tools and runtime environments to help embedded software developers efficiently program from concept to production. Xilinx provides developers with an Eclipse-based IDE called the Xilinx Software Development Kit (SDK), which includes an editor, compiler, debugger, drivers, and multiple libraries for Zynq SoCs or FPGAs containing Xilinx's 32-bit MicroBlaze™ soft core. The environment is ready to use out of the box and supports a variety of advanced features, such as security and virtualization software drivers built on Xilinx's unique Zynq SoC and MPSoC. This allows developers to build intelligent, secure, and truly differentiated connected systems.

Xilinx provides a full set of open source resources to develop, boot, run, debug and maintain Linux applications running on Xilinx SoC or emulation platforms. Xilinx provides example applications, kernel builds, Yocto recipes, multi-processing and real-time solutions, drivers and forums, and community links. Linux open source developers will find a very comfortable environment in which to learn and develop, and interact with other users with the same interests and needs.

In addition to providing developers with new SDx development environments and SDKs, Xilinx has also built strong alliances over the past decade with many companies that already have well-established development environments that serve developers in specific market segments.

National Instruments (NI) (Austin, Texas, USA) provides hardware development platforms that are popular with control and test system innovators. Xilinx FPGAs and Zynq SoCs power the NI RIO platform. NI's LabVIEW development environment is a user-friendly graphical program that runs Xilinx's Vivado Design Suite, so NI customers don't need to know any FPGA design details, and some customers may not even know that Xilinx devices are at the heart of the RIO platform. But they can simply program the system in the LabVIEW environment and let NI's hardware accelerate the performance of the design implementation they develop.

MathWorks® (Natick, MA, USA) has provided FPGA support in its MATLAB®, Simulink®, HDL Coder™, and Embedded Coder® for more than a decade, and Xilinx's ISE® and Vivado tools can run in them fully automatically. This allows users (mainly algorithm developers with math skills) to easily run their algorithms on FPGA architectures while developing them and significantly improve algorithm performance.

Xilinx added an FPGA architecture-level tool called System Generator to its ISE development environment more than a decade ago and, more recently, to the Vivado Design Suite to enable teams with FPGA knowledge to tweak designs to further improve algorithm performance. This combination of MathWorks and Xilinx technology has helped the company’s customers create many innovative products.

Many Xilinx Alliance members, including ARM, Lauterbach, Yokogawa Digital Computer Corp and Kyoto Microcomputer Corp, provide development tools that support SDx and Alliance environments. In terms of OS and middleware support, Xilinx and Alliance members offer customers a variety of software options, such as Linux, RTOS, bare metal, and even solutions including hypervisors and Trust-Zone kernel support to meet confidentiality and security needs.