Renesas Electronics Unveils First-Ever PCIe 6.0 Clock Solution to Help Usher in a New Era of High-Performance Computing
Since its launch in 2003, PCI Express (PCIe for short) has become one of the most widely used high-performance peripheral interfaces in the world. Its arrival is essentially to solve the speed and noise problems of PCI, PCI-X and AGP.
Different from the bus structure of PCI, PCI-X and AGP, PCIe, as the expansion bus of the South Bridge, adopts a point-to-point serial structure, which means that PCIe can only connect one device physically and transmit information by using differential signals. The benefit of this serial structure is that the original half-duplex communication is naturally upgraded to full-duplex, and the same content is transmitted through a positive and negative mirror mode, so noise interference can be quickly discovered and corrected, so the transmission frequency is greatly improved (in parallel transmission, the noise interference between parallel lines will increase with the increase of transmission rate until it cannot be crossed), and the transmission rate is also increased.
Figure | PCIe location diagram
Of course, the demand is always changing. In order to further improve the transmission rate, PCIe has also gone through multiple iterations. From a technical point of view, PCIe 6.0 is the most significant evolution since the advent of PCIe. Compared with previous generations, PCIe 6.0 uses PAM4 four-level pulse amplitude modulation, and the data transmission rate has increased to 64GT/s, achieving the goal of doubling across generations.
So, what drives the PCIe standard into the 6.0 era? As we all know, with the popularization of 5G technology, the Internet of Things will enter an explosive stage, accompanied by the generation of massive data. How to better store, transmit and process data will become one of the challenges in the future. For application scenarios that require low latency and high bandwidth, such as data centers/cloud computing, networks and high-speed industries, PCIe 6.0 is a precautionary layout for information transmission.
Figure | Three basic PCIe reference clock architectures
As the "heart" of new devices in data centers, high-speed networks and other applications, PCIe clock devices will play a very important role. As an excellent supplier of advanced clock solutions in the industry, Renesas Electronics has taken the lead in launching PCIe Gen1, Gen2, Gen3, Gen4, Gen5 and Gen6 clock solutions in the PCI Express clock industry, including ultra-low power PCI Express clock generators (1.8V/1.5V), clock buffers and multiplexers that meet strict standards. These solutions also support ultra-low power LP-HCSL outputs, which save up to 85% of power consumption compared to standard HCSL outputs, and support the integration of multiple PLLs in a single device, saving power while also saving circuit board space.
Recently, Renesas Electronics launched 11 new PCIe Gen6 clock buffers RC190xx and 4 new PCIe Gen6 multiplexers RC192xx , with extremely low additional jitter performance of only 4fs RMS. The low-jitter 9SQ440, 9FGV1002 and 9FGV1006 clock generators, as well as a variety of analog and power products, can provide customers with a complete PCIe Gen6 clock solution to better support higher-performance systems such as data centers, high-performance computing, and high-speed industries.
Readers interested in PCIe jitter specifications can view the following related video: Comparison of PCIe3.0-PCIe6.0 internal jitter filter and 12k-20MHz jitter filter.