Warning! Your RF device needs system-level ESD protection

Mobile phone designers are constantly faced with the challenge of when and how to address this natural phenomenon. Why is system-level ESD protection so important? How can test models and strategies for improving system-level ESD protection in mobile devices be developed?

The human body and clothing can store 500 V to 2,500 V of electrostatic charge in a single day, but humans can only feel ESD pulses of 3,000 to 4,000 V. This is far above the level at which electronic circuits can be damaged, even though humans cannot detect it.

Designers must address ESD issues from multiple perspectives, and for component manufacturers, both during the design phase and at the end of their design work. In short, ESD protection requires a multifaceted approach.

Typically, integrated circuit (IC) manufacturers design, test, and certify their ICs to ESD industry standards. This prevents physical damage during IC production or assembly on PC boards. Two common tests for ESD include:

• Human Body Model (HBM) . This test simulates an ESD event in which a human body discharges the accumulated static electricity by contacting an IC. It is simulated using a charged 100 pF capacitor and a 1.5 kΩ discharge resistor.

• Charged Device Model (CDM) . This test simulates the charging and discharging events that occur in production equipment and processes. The device acquires a charge during some triboelectric process or electrostatic induction and then suddenly contacts a grounded object or surface.

While device-level testing helps measure the ESD robustness of an IC, system-level testing measures the protection of electronic devices in the field (i.e., original equipment manufacturer [OEM] equipment or end product).

To better understand the ESD protection required for the end product, OEMs should design with a system-level ESD approach and then test the end product to the International Electrotechnical Commission (IEC) ESD standard 61000-4-2. IEC 61000-4-2 is considered the industry standard for ESD testing and rating of end products. This testing determines the system's vulnerability to external ESD events in the field.

The following graph compares the energy and peak current of the three pulses:

• System level IEC 61000-4-2

• Device-level HBM

• Device-level CDM

IEC ESD event pulses are obviously stronger and therefore more difficult for devices in a system to pass. While device-level testing (HBM and CDM) is useful and provides a baseline for ESD robustness, survivability cannot always be determined during system-level IEC testing.

To further illustrate this concept, the table below shows the difference between component testing and system-level IEC testing. As you can see, the difference is huge and the system stress level is much higher. Bottom line: system design must meet more stringent requirements than device-level design.

Conducting system-level ESD testing during the development phase can be problematic. For example, testing ESD on evaluation/incomplete board assemblies is not representative of all situations. The results on these assemblies do not guarantee the final results on the complete system.

Device-level ESD testing (i.e. HBM and CDM) is designed to produce repeatable and reproducible results for discrete components in the factory with proper ESD control. This is known as the ESD Protection Area (EPA) . However, these tests are not designed to address the full range of product-level ESD events that occur in the real world outside the scope of the EPA.

Instead, the key to ESD-robust system design is to consider the effects of ESD in the system. To gain a system-level perspective, designers must understand and address the following issues:

• System-level stress events and their impact on the entire product. Device-level ESD test results provide very little information for system ESD design because they do not reflect what the electronic device experienced during an IEC ESD event.

• Board-level interactions in the system and transient behavior of pins in contact with the outside of the electronic component under ESD stress.

• Efficient characterization methods, such as component-level transmission line pulse (TLP) data , for analyzing IC, board, and system interactions.

System-level ESD protection strategy depends on the physical design, product requirements, and product cost.

System Efficient ESD Design (SEED) is a system-level approach that considers the transient response of all components in the system. The SEED approach also includes the physical effects of IEC stress applied to the external ports of the PC board on the IC pins.

SEED is a co-design methodology for on-board and on-chip ESD protection. With SEED, you can analyze and implement system-level ESD robustness. The methodology requires a comprehensive understanding of the interaction between external ESD pulses, the complete system-level board design, and device pin characteristics during an ESD stress event.

The SEED method is the best way to achieve symmetrical and robust system-level ESD protection. As shown in the figure below, SEED designs system-level ESD protection using the following information:

• Quasi-static TLP current-voltage (IV) curve data

• Transient simulation

• S Parameters PC Board Data

• IC IV Circuit Measurements