How to achieve a more "mini" phased array radar platform? Learn about integrated transceivers
Phased array radar systems utilize multiple transmit and receive channels to function properly. Historically, these platforms have been built using discrete transmit and receive integrated circuits (ICs). These systems use separate chips for the digital-to-analog converters (DACs) in the transmit (Tx) circuitry and the analog-to-digital converters (ADCs) in the receive (Rx) circuitry. This discrete approach makes many systems large, expensive, and power-hungry to get the number of channels required to deliver the required functionality. These systems also typically take a long time to get to market due to the complex manufacturing and calibration processes.
A more recent approach has been to use integrated transceivers to combine many of the functions that were once considered disparate into a single IC. These ICs enable small size, low power and low cost, high channel count phased array radar systems with faster time to market.
Integrated transceivers, such as the one shown in Figure 1, combine multiple functions onto a single IC. For example, the new transceiver combines a DAC, ADC, local oscillator (LO) synthesizer, microprocessor, mixer, and more into a 12 mm × 12 mm single-chip product. In addition, two receive channels and two transmit channels are integrated, along with multiple digital signal processing (DSP) components to achieve the instantaneous bandwidth required by the system. An application programming interface (API) is also provided for operating the transceiver on the customer's software platform. Gain and attenuation control can be implemented using the on-chip front-end network. Built-in initialization and tracking calibration routines are used to provide the performance required for many communications and military applications.
Figure 1. The ADRV9009 is an example of an integrated transceiver that combines multiple functions into a single IC.
These integrated transceivers are able to create all the clock signals required for the transmitter and receiver by injecting a reference clock signal called REF_CLK. All the clocks required for DAC/ADC sampling, LO generation, and microprocessor clocking are then synthesized by an on-chip phase-locked loop (PLL). If the internal LO phase noise is not sufficient for the customer's application requirements, the user has the option of injecting a low phase noise LO externally.
Data from the transceiver is transmitted via a standardized JESD204b high-speed serial data interface. This interface supports receiving and sending large amounts of data simultaneously. The new integrated transceiver solution can help provide interface IP to help customers accelerate time to market. If deterministic latency and data synchronization are required, users can take advantage of the built-in multi-chip synchronization (MCS) feature and issue a SYS_REF signal as the master timing reference for the initial channel alignment sequence (ILAS).
In addition, the built-in RFPLL phase synchronization feature can be used to set the LO phase of the transmit or receive channel to be deterministic relative to the master reference phase. By using the MCS and RFPLL phase synchronization features, phase alignment can be ensured when initializing the part, frequency tuning, or turning the transmit and receive channels on and off. Figure 2 shows an example of a new integrated transceiver that provides deterministic phase and supports all of these features.
Figure 2. The built-in RFPLL phase synchronization feature provides a deterministic phase relationship between the system and the master reference source.
If the system requires more than two receivers and two transmitters, the user can still use multiple integrated transceivers and benefit from the small size achieved by the single-chip receive and transmit channels. An example of this technique is shown in Figure 3. Multiple integrated transceivers can be synchronized by using concurrent SYS_REF pulses to trigger the internal dividers of all ICs at the same time. These SYS_REF pulses can be issued by the clock chip or baseband processor with programmable delays that can compensate for delay variations introduced by path length mismatches between ICs. This allows deterministic delays for data paths and multiple LOs across multiple chips.
Figure 3. Multiple integrated transceivers can be used to increase the channel count of a system.
Increasing the number of channels through the use of synchronized integrated transceivers makes these devices the backbone of phased array radar platforms. The use of multiple integrated transceivers has demonstrated system-level improvements in dynamic range, spurious, and phase noise when combined with phase- and amplitude-aligned transmit and receive channels.
On-chip DSP features, such as numerically controlled oscillators (NCOs) and digital upconverters, or digital downconverters (DDCs), now enable system-level spurious decorrelation methods within a single IC.
Improvements in system-level noise spectral density (NSD) and spurious performance have been demonstrated by combining transceiver channels using multiple integrated transceivers. This improves the dynamic range of a phased array radar system by lowering the effective noise floor of the system while maintaining the full functionality of the channels. Figure 4 shows system-level measurements after integrating up to eight integrated transceiver receive channels, effectively increasing the number of bits in a phased array system. Note that the NSD and calculated noise floor (shown as red lines in each figure) increase by 6 dB when going from one to eight channels. This is because, although there are eight total channels, there are only four different and uncorrelated LOs in the four integrated transceivers used to create those eight channels (that is, N LO =4). This results in an improvement of
The results are close to experimental results provided by integrated transceivers. In addition, the unwanted imaging frequencies are aggregated in an uncorrelated manner, resulting in improved system-level spurious performance. Further improvements are achieved as the number of channels increases, enabling scalable systems.
Figure 4. Integrating the receive channel using the ADRV9009 integrated transceiver reduces noise spectral density and improves dynamic range.
Additionally, the phase noise of a phased array system can be improved after aligning the phases and integrating multiple integrated transceiver channels. The top three curves in Figure 5 show the measured results, which show the improved phase noise performance after combining eight channels using the internal LOs of four integrated transceiver ICs. To repeat, when there are four different and uncorrelated LOs (that is, N LO = 4), the phase noise increases by 6 dB when going from one to eight transmit channels. Increasing the number of channels can further increase the phase noise of a phased array radar system. Alternatively, an external LO can be injected into each subarray of N integrated transceivers and the initial phase noise can be improved at the subarray level (as shown by the blue curve in Figure 5).
However, in this case, the elements in the subarray will be correlated because they all share the same LO source, and thus cannot provide channel aggregation improvement in the subarray by itself. For the external LO phase noise data shown in Figure 5, a Rohde & Schwarz SMA100B signal generator was used as the external LO source.
Figure 5. Integrating the transmit channels of multiple ADRV9009s improves system-level phase noise performance when using the internal LO. Injecting an external LO improves the initial phase noise of the subarray.
Integrated DSP features such as NCOs, digital phase shifters, and DUC/DDCs allow baseband phase and frequency shifts to be implemented in the digital domain, which in turn allows digital beamforming to be implemented in multi-channel, integrated transceiver-based phased array radar systems. By integrating multiple functions onto a single IC, the system is now able to achieve antenna lattice spacing with integrated transceivers in many relevant phased array applications. Increasing the number of channels with more transceivers generally results in narrower beams, but in a larger system. However, the system is now proportionally smaller than in the past with the integration of multiple functions onto a single IC. Using MATLAB® to simulate the radiation pattern, Figure 6 shows how the beam narrows and the theoretical lobe amplitude deepens as the number of channels increases from 2 3 to N = 2 10. The actual power null will be determined in the antenna design.
Figure 6. DSP features can now digitally shift phase using on-chip NCOs and DDCs/DUCs. Increasing the number of channels and optimizing the phase shift will allow the integrated transceiver to form narrower beams.
The integration of multiple digital and analog functions in a single IC enables smaller phased array radar systems. These systems support the implementation of digital beamforming and hybrid beamforming, depending on the system specifications. System-level performance improvements have been demonstrated using the ADRV9009 from ADI. These integrated devices enable many new systems to use the same hardware to run multiple applications.
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