Type-C new technology and interface chip testing for simplified connection
* The text is about 6,000 words, and the estimated reading time is 20 minutes
Since the USB-IF Association released the new generation interface Type-C in 2014, its excellent performance, simple connection, scalability and multi-function immediately attracted the attention of consumers throughout the industry. In recent years, Type-C technology has flourished in the consumer electronics industry with the above advantages. Its characteristics are summarized as follows:
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Minimalist connection: Compared with the previous A/B ports, it can achieve a small size of about 8.3mm x 2.5mm, flat and thin, and supports positive and negative connection;
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Scalability: can be used for different terminal devices such as computers, mobile phones, monitors, USB flash drives, docking stations, etc.
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Versatility: Supports USB 2.0, USB 3.2, USB4, DP 1.4a, DP 2.0/2.1, PCIe and PD functions;
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Diverse ecosystem: including chips and terminal products, such as desktops and laptops, mobile phones, docking stations, USB flash drives, monitors, embedded boards, passive cables, active cables, etc.
Since the USB-IF Association first released the USB Type-C technical specification in August 2014 to support USB2.0, 3.1 and PD 2.0, after years of iterative updates, Type-C can now support new technologies such as USB4 and DP 2.1. The complexity of its research and development and testing has also increased significantly. In the following section, we will introduce an overview of the testing of new technologies such as USB4 and DP 2.1 based on Type-C.
USB4 Technology
When talking about Type-C, let's talk about USB4 technology first. The USB-IF Association announced the development of new technology in March 2019 and released the USB4 specification in September of the same year. Such a short time was due to the reference to the TBT3 technology contributed by Intel (Keysight Technology has released software and hardware solutions related to TBT testing many years ago).
USB4 is an interconnection-oriented technology and is more complex than USB 3.2 technology. First, existing USB Type-C cables can be used, but attention should be paid to the difference in loss caused by different cables. If 2-channel bonding/40Gbps is to be supported, USB4-certified cables must be used. Second, tunnel technology is used to carry multiple protocols and support mechanisms such as time synchronization and dynamic bandwidth allocation. Third, it is compatible with USB 3.2, USB 2.0, etc. Fourth, higher speeds make the transceiver architecture more complex, which is reflected in the complex transmit emphasis and receive equalization mechanisms of the electrical sublayer. The logic sublayer uses precoder and fec technology to reduce the sudden continuous errors that may be caused by DFE and improve robustness.
Let's introduce the USB Type-C connector and cable, which carry USB4 data and are an important part of design and testing. In August 2014, the USB-IF Association first released the USB Type-C technical specification, supporting USB 2.0, USB 3.1 and PD2.0. After years of iterative updates, the v2.0 version was released in August 2019 to add support for USB4, and the v2.1 version was released in May 2021 to add support for USB PD 3.1 extended power capability.
Type-C connectors and cables play a very important role in high-speed transceiver interconnection. The following shows the characteristics of USB Type-C cables and traditional USB cables in terms of power supply, signal rate, and cable length. In terms of power supply, the current of USB Type-C connector can reach 5A. If the Type-C cable supports the USB PD standard power range, it can reach 3A/60W. If it supports the extended power range (must have an electronic label), it can reach 5A/240W. In terms of cable type, in order to facilitate the expansion of USB4 terminal products to support display and other applications, active cables are implemented by using redriver or retimer to extend the transmission distance and improve user experience. In terms of signal rate, the higher the rate, the greater the relative loss. The transmission distance of the same material cable becomes shorter. USB 2.0 Type-C cable supports 480Mbps and can achieve a transmission distance of up to 4m. The USB4 rate is increased to single lane 20Gbps, and the transmission distance using passive cables is only 0.8m. In addition, the same transmission rate USB 3.2 Gen2 10Gbps and USB4 Gen2 10Gbps have different transmission distances due to different system link loss budgets that follow the standard.
*Mini B:500mA
Figure: Comparison between USB Type-C and traditional USB cables
Finally, let's talk about specifications and testing. The USB4 specification provides an important reference for chip and product design. In order to ensure good quality, improve stability, ensure compatibility, and support new functions, certification is required. Certification requires a variety of consistency tests (refer to "USB4 Certification Test"), and USB4 physical layer electrical consistency testing is an important part of it. The consistency test specification CTS has gone through different versions 0.96, 1.0, and 1.01. The latest version is version 1.02 released in July 2021, which updated the Clock Switch test item.
Figure: USB4 certification test (from www.usb-if.org)
USB4 working principle and testing difficulties
Reading progress: 20 %
USB4 is a technology that achieves interconnection through USB Type-C. It supports up to 6 Routers in a tree topology, and implements USB3, PCIE, DP and other protocol transmissions through tunneling technology. It is also compatible with products using TBT3 technology. Therefore, USB4 technology is complex.
Compared with USB 3.2, USB4 is similar in that both support data exchange between the host and various peripherals, but different in that USB4 allows the host to establish data exchange between peripherals. USB4 is connection-oriented and implements tunnel architecture. It puts USB3, DP, PCIE and other data packets into the tunnel through the protocol adapter. Each protocol can work independently (via the transport layer and physical layer), and can also implement bandwidth management through CM (Connection Manager) and time synchronization through TMU. Router is the core of USB4, and there are two types: Host router and Device router, including a point-to-point configurable switch that can establish a unidirectional logical connection between the adapters of both parties.
Taking a typical USB4 Host as an example, the internal components include 1 Host Router, 1 USB 2.0 Host, 1 USB 3.2 Host, and 1 DisplayPort Source. It can optionally support PCIE controller. The interface rate must support 20G Gen2 x2 and can optionally support 40G Gen3x2. The external physical interface typically supports 2 Ports, at least one of which must support DFP. It can functionally support Tunnel technology to carry DP, PCIe, and USB3.0 data packets from DP source, PCIe Controller, and SuperSpeed Host, support USB2.0 Host function, and can optionally be compatible with TBT3 products and USB Type-C Alternate Mode products (refer to "USB 2.0/USB 3.2/USB4 Data Technology Comparison"). USB4 has complex functions.
There are many difficulties in conducting physical layer electrical consistency testing on products that use complex technologies. Refer to "USB4 Technology Changes", which involve test points, transceiver architecture, test mode, test code pattern, test parameters, and there are also test challenges brought about by changes in cables/connectors.
First , it is necessary to identify the electrical consistency test points. TP1 is the IC chip pin, which is usually not directly detectable. For the transmission consistency test, there is only one test networking environment, TP2 (taking the terminal PC as an example, measured with a plug fixture) and TP3 (the S parameter file is embedded in the oscilloscope, supporting the S parameters of 2m and 0.8m cables). For the reception consistency test, TP3' and TP3 need to be selected. Incorrect selection of test points will affect the test results. The following is a description of the test points mentioned in the USB4 specification:
Figure: USB4 physical layer electrical consistency test points
Second , the physical electrical sublayer transmit emphasis and receive equalization are more complex. Transmission supports 16 different presets, implemented through a 3-coefficient FIR filter, and reception supports CTLE and DFE. The reference CTLE supports 10 templates to "compensate" for high-frequency losses. The reference DFE is a 1-tap filter that can correct the impact of inter-symbol interference. The tap adjustment coefficient limits the adjustment voltage amplitude to within 50mV.
Third , the test modes are different. Compared with USB 3.2, USB4 products require the hardware controller to use the USB ETT software tool to configure the DUT to generate test code patterns and implement bit error rate testing.
Fourth , the test code types are complex. Compared with USB 3.2, USB4 products must support and be able to generate test code types such as SQ128, PRBS15, PRBS31, SQ2, SQ4, and Electrical Idle mode.
Fifth , the test parameters are complex. Compared with USB 3.2, USB4 product testing requires time domain, frequency domain and BER tests. From the perspective of time domain, it supports 10Gbps and 20Gbps, and 10.3125bps and 20.625Gbps are optional. The LFPS pattern test is cancelled, and the RF cable from the fixture to the oscilloscope needs to be de-embedded. Due to the complex transceiver architecture, the Tx consistency test needs to verify the Pre-shoot/de-emphasis of 16 presets, and P15 also needs to verify Swing, add UI, SSC Phase Deviation (Phase jitter), Tx Freq Variation Training (only required when including retimer, to examine the local clock and recovery clock switching), TJ (to be extrapolated to 1E-13), UJ, UDJ, LF-UDJ, DDJ, DCD Jitter (EOJ), Eye mask (Gen3 TP3 eye opening is 98mV/27ps, which has high requirements for instrument noise floor and jitter), and add AC Common mode.
From the frequency domain perspective, SDD11 and SCC11 are added. SDD11 represents differential return loss. The Tx and Rx differential impedances must be constrained through board-level design. In addition to AC coupling capacitors and ground discharge resistors, consumer electronic products also add protection devices, which poses a challenge to this test. SCC11 represents common-mode return loss, and the single-ended impedance must be constrained and considered.
From the perspective of BER testing, during the Rx consistency test, the SBTRX signal needs to be used to configure the DUT to enter the test mode and enable the built-in error counter. The test needs to build different loss scenarios of case 1 and case 2. This loss needs to be calibrated through the vector network instrument E5080B with a frequency range of 20GHz. The real-time oscilloscope calibrates the pressure parameters in different scenarios of case 1 and case 2. In the case 1 scenario, the Preset with the smallest DDJ is found and used to calibrate AC CMSI, RJ, PJ and verify TJ (RJ or PJ can be adjusted) to finally find the parameters of the minimum eye opening that meets the standard (adjustable amplitude). The case 2 scenario is similar. In the case 1 and case 2 scenarios, it is connected to the DUT for uncoded bit error rate testing. Here, the bit error rate is calculated by reading the internal error counter of the DUT to see if it meets the 10-12 requirement.
Sixth , the same physical port supports different standards and different line losses, which is a great challenge. Speaking of loss, comparing USB 3.2 and USB4 losses (refer to "USB 3.2 and USB4 loss distribution comparison"), taking Type-C to Type-C interconnection as an example, USB 3.2 10G requires a target total loss of 23 dB, and the Host/Cable/Device distribution is 8.5, 6, 8.5. The target total loss of USB4 10G is the same, and the Host/Cable/Device distribution is different (5.5, 12, 5.5). The target loss of USB4 20G is 22.5, and the Host/Cable/Device distribution is 7.5, 7.5, 7.5. Higher speeds must overcome the impact of "long links". The link includes DIE loads, packages, vias, routing, connectors, cables, etc., which will introduce impedance matching, inter-symbol interference, crosstalk, etc., and the design of chips, boards, etc. is challenging.
Figure: USB 2.0/USB 3.2/USB4 data technology comparison (from www.usb-if.org)
|
Type\IL(Type-C) |
Host* |
Cable |
Device* |
Total |
|
USB 3.2 Gen2 (10 Gbps) |
8.5 dB |
6 dB |
8.5 dB |
23 dB |
|
USB4 Gen2 (10 Gbps) |
5.5 dB |
12 dB |
5.5 dB |
23 dB |
|
USB4 Gen3 (20 Gbps) |
7.5 dB |
7.5 dB |
7.5 dB |
22.5 dB |
*Host/Device loss involves everything from the die to the connector
Figure: USB 3.2 and UBS4 target loss comparison
Figure: USB4 technology changes
USB4 physical layer test solution
Reading progress: 50 %
When it comes to USB4 physical layer electrical consistency testing, the sending, receiving, and interconnection channels all require attention.
The USB4 transmitter consistency test needs to be measured and calculated at TP2 and TP3. Compared with USB 3.2, in addition to the eye diagram, SSC, TJ, RJ, and DJ, it is worth noting that the USB4 specification uses a different jitter decomposition method: TJ is decomposed into UJ (calculation/TJ-DDJ) and DDJ (measurement), and UJ is decomposed into RJ (measurement) and UDJ (calculation/UJ-RJ). In addition, there are related test items such as DCD jitter (EOJ), LF-UDJ, Phase Jitter, Tx Freq Variation, Sdd11/Scc11, etc. The following figure is a test network diagram of the transmitter:
Figure: USB4 transmitter electrical consistency test network
Figure: USB4 port return loss test network
The D9040USBC software developed by Keysight Technologies supports different types of DUTs such as Host and Device, supports 1 port or 2 ports, each port can support 1 lane or 2 lanes, supports 10Gb/s, 20Gb/s and TBT3's 10.3125Gb/s, 20.625Gb/s. It not only supports debugging, but also can be used with USB4 controller and USB ETT tool software for automated testing, greatly improving efficiency, and can output reports containing test margin, test threshold and reference test source.
For USB4 receiver consistency test, the automatic calibration and testing platform based on M8020A/M8040A BER and N5991U40A software supports different types of DUTs, including USB4 Router, TBT3 Host, and TBT3 Device. It supports 4 rates, including 10Gb/s, 20Gb/s, 10.3125Gb/s, and 20.625Gb/s. It supports case 1 and case 2 scenarios, BER test, Multi Error-Busrt test, Signal Frequency Variation Traing test, etc. In addition, it also supports expert mode, which can realize commissioning, jitter tolerance, sensitivity, customized BER test, etc. The following is the test network diagram of the receiver:
Figure: USB4 receiver electrical consistency test network
When calibrating and receiving BER tests, USB4 has many differences compared to USB 3.2. A new AC CMSI noise (100mVpp@400MHz) stress parameter is added, and the SSC parameter (32kHz@+300ppm~-5300ppm) is modified. It supports case 1 and case 2 constructed with two passive cables of 2m and 0.8m. The channel loss corresponding to the two scenarios is 18~19dB@5GHz and 16~17dB@10GHz, respectively. A 20GHz vector network analyzer is required for calibration. In case 1 and case 2, SSC calibration stress parameters are enabled, involving DDJ, AC CMSI, RJ, PJ, TJ and Eye. Accurate calibration is the basis of the test, and the BER test method is also different. The calibration parameters are called, and the bit error meter uses the preset selected in the calibration to communicate with the DUT. The USB4 controller uses the SBTRX signal through the USB ETT software to cooperate with the high-speed link for link negotiation. The bit error meter selects the appropriate preset according to the negotiation situation, and then checks the internal error of the DUT. Check whether the counter is normal and complete the counter reset, and finally perform the bit error rate test (complete PJ: 1MHz/2MHz/10MHz/50MHz/100MHz@1E-12).
In addition to the electrical sublayer, the physical layer also has a logical sublayer. For chip and terminal product debugging, it is also necessary to understand the circuit power-on lane initialization and link establishment. This requires familiarity with the state machine of the logical sublayer (refer to "USB4 logical sublayer state machine"), which includes 6 states: Disabled, CLd, Training, CL0, Lane Bonding, and Low Power. Among them, CLd involves lane initialization. Sideband Channel (SBTx and SBRx signals/1Mbps) is initialized with the help of 3 types of transactions. The initialization includes 5 stages: P1-initial condition determination, P2-Router detection, P3-USB4 port feature determination, P4-lane parameter synchronization and transmission start, P5-lane equalization.
Figure: USB4 logical sublayer state machine
Based on the MXR/V/Z/UXR oscilloscope platform, the analysis and trigger setting of the USB4 logic sublayer are realized with the help of N7019A hardware and D9010USBP software, as shown below:
Figure: USB4.0 protocol analysis and triggering
The types and signal types of consistency tests for cables and connectors are complex and diverse, including not only high-speed signals such as USB 2.0, USB 3.2, and USB4, but also low-speed signals such as CC, SBU, and VBUS. The key indicators that characterize high-speed signals include ILFit (insertion loss fitting), IMR (integrated multiple reflections), IRL (integrated return loss), IXT (integrated crosstalk), etc., which are different from the common S parameters of cables, such as IL and RL, and involve complex mathematical calculations.
In addition, the COM technology is introduced based on the IEEE 802.3 standard to evaluate through the SNR indicator. According to the "USB Type-C Cable and Connector Specification" and "USB Type-C Connectors and Cable Assemblies Compliance Document", Keysight Technologies launched the USB Type-C cable and connector compliance test solution based on the E5080B 4 Ports/P5000 USB VNA/M9804A Multiport VNA.
Figure: USB Type-C cable and connector consistency test solution
DP2.1 Technology
Reading progress: 70 %
In addition to supporting USB4 (Tunnel technology only supports DP1.4a/HBR3), the Type-C interface can also support DP2.1 for audio and video transmission. The initiator of DisplayPort is VESA. Genesis, Intel, AMD, Analogix, HP, Dell and Keysight have actively participated in the formulation of the standard. Its main advantages are very high data rate, convenient connection, perfect content protection and data transmission based on packet switching. It supports 4 pairs of differential channels and can cascade up to 32 displays.
The communication architecture based on DP technology requires the participation of high-speed links, low-speed Aux channels and HPD (required for full-size DP interfaces). Aux Channel is a differential signal that operates at a bidirectional/1Mbps rate to perform link management and test mode control. It can obtain EDID and DPCD information, and link training still requires the participation of high-speed channels. DP2.1 supports 1, 2 or 4 lanes, optionally supports SSC, and has 7 different rates. With the help of Type-C connector, it can support high-speed UHBR13.5 and UHBR20. The encoding efficiency is increased to 97% using 128b/132b encoding. At the same time, the electrical architecture of the physical layer of the receiver and transmitter has become complex. The transmission uses 3-tap FFE to achieve 16 different presets, and the reception uses a combination of CTLE and DFE to overcome high-frequency losses. CTLE supports 10 different DC gain level settings. Considering the transmission of FFE, there are up to 160 combinations.
DisplayPort physical layer electrical consistency test involves Source, Sink end test, connector/cable.
The following figure is a connection diagram for DisplayPort Source transmitter consistency test. Similar to other high-speed serial bus interface transmitter consistency test solutions, it mainly consists of a fixture, a low-loss phase-matched cable (or an SMA/2.92mm probe kit), and a real-time oscilloscope.
According to the CTS test specification requirements (DP2.1 Spec and CTS have not yet been officially released), first of all, the test must clarify the consistency test points, the Source is tested in TP2, and the oscilloscope must support embedded S parameters and equalization capabilities to achieve TP3 and equalized data processing. Secondly, the device under test is required to support different rates, such as UHBR10/13.5/20 rates, support test patterns, such as PRBS15, PRBS31, SQ128, support SSC, and support P0~P15 Presets. Thirdly, the test parameters must be clarified and traversed through 3 different rates, including TP2 related: Rise time fall time, EQ (PS/DE/Swing-P15), Preset Cal (P0~P15), UI, Main Link Frequency, SSC, Voltage, AC Common Mode, TJ, RJ, UJ, UDJ, ISI, DCD, DDJ, LFUDJ, Eye; TP3 related: Eye-TP3, Preset&Eq Cal-TP3_EQ, TJ-TP3_EQ, RJ-TP3_EQ, UJ-TP3_EQ, DDJ-TP3_EQ, ISI-TP3_EQ.
In addition to chip manufacturers with special software that can configure DUT, the industry usually uses a reference AUX controller (DPR-100, UCD-323, etc.) certified by the association, and configures the oscilloscope's DisplayPort consistency analysis software D9040DPPPC/D9042DPPC to communicate with DUT through the AUX channel, allowing the device under test to generate the corresponding response rate and test pattern at the right time, thus forming a fully automated closed-loop test. With multiple test rates, multiple patterns, and multiple parameters, it still takes a long time to complete all 4 lane tests with an oscilloscope alone. Keysight Technologies has introduced a measurement decoupling method, with sequential acquisition of the oscilloscope and parallel data processing through more external computers, reducing processing time and improving efficiency.
Figure: DP consistency test points and description
Figure: DP Source electrical consistency test network diagram
Figure: Measurement decoupling
For the DP Sink, electrical consistency testing is required. As a receiver, it requires a device that can stimulate signals and has adjustable stress parameters. Keysight's M8000 series BERT has a built-in calibrated jitter source that can directly generate jitter signals, such as RJ, PJ/SJ, ISI jitter and SSC signals, and can also support the injection of AC CMSI interference. To ensure that the Stressed Signal passes through different test accessories and test fixtures and strictly meets the CTS test specification requirements at the test point of the Sink device, it is necessary to calibrate the signal with a high-bandwidth oscilloscope before testing the Sink device. Keysight's N5991DP2A DP2.0 Sink consistency test software can accurately control the output of the oscilloscope and BERT through a graphical interface, and fully automate complete signal calibration. When performing a Sink test, the N5991DP2A software controls the BERT to generate a corresponding stressed code sequence and injects it into the Sink device through the fixture. At the same time, it controls the Aux Controller to complete the link negotiation, Symbol lock and BER test (there is an Error Counter in the DUT) with the Sink device. Therefore, a complete DP Sink test solution requires a BERT, a high-bandwidth oscilloscope, automated control software, an Aux Controller and necessary test accessories/fixtures, as shown below.
Figure: DP Sink test network
DP souce and sink are interconnected, and connectors/cables are indispensable. Network instrument reference specifications are also required for consistency testing. When the rate is increased to 10G, 10.3125G, and 20G, the key indicators in the time domain and frequency domain of high-speed testing can still refer to ILFit (insertion loss fitting), IMR (integrated multiple reflections), IRL (integrated return loss), IXT (integrated crosstalk), etc. mentioned in USB Type-C.
The VESA DP2.1 specification also mentions that enhanced mini DP and full-size DP connections can improve link performance and support higher rates. Currently, the DP2.1 consistency test specification is still being developed, and Keysight Technologies is participating in the relevant verification tests. The newly released D9042DDPC and N5991DP2A can support UHBR rates. In the face of higher-rate interface technologies, more complex transceiver architectures, and newly added test parameters, Keysight Technologies can provide a comprehensive solution from simulation, debugging, physical layer electrical consistency testing to interconnect channel testing, as shown in the following figure:
Figure: Keysight Technologies Type-C overall test solution block diagram
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We are committed to helping enterprises, service providers and government customers accelerate innovation and create a secure and connected world. Since the founding of HP in 1939, Keysight Technologies has been operating independently as a new electronic test and measurement company on November 1, 2014. We continue to uphold the same entrepreneurial spirit and passion to start a new journey, inspire global innovators and help them achieve goals beyond imagination. Our solutions are designed to help customers innovate in 5G, automotive, IoT, network security and other fields.
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