How to Provide Overcurrent Protection for Buck Regulators

Synchronous buck regulators are widely used in industrial and infrastructure applications to step down 12V power rails to load point inputs as low as 0.6V for microcontrollers, FPGAs, memory, and peripheral I/Os. To prevent these switching regulators from being damaged by excessive current, overcurrent protection (OCP) is critical. Cycle-by-cycle current limiting is generally used because of its fast response time. This scheme allows the switching regulator to continue operating at the maximum load current, but it also generates excessive heat and may reduce system reliability. Using secondary protection schemes such as hiccup mode and latch-off mode can solve reliability issues and improve mean time between failures (MTBF).

This article discusses several popular OCP schemes and explains how they work and how they are implemented in a buck regulator. We will also discuss practical considerations that power supply designers face to help them make the most appropriate choice for their application.

Overcurrent protection with cycle-by-cycle current limiting

Current mode control (CMC) buck converters have become very popular in recent years because of their many advantages. One of the main advantages is that they provide inherent cycle-by-cycle current limiting simply by clamping the COMP voltage. Figure 1 shows the block diagram of a peak CMC buck converter, which is used as an example to explain various OCP schemes.

Figure 1. Peak CMC buck converter block diagram.

The inductor current information is required to achieve current limiting. The most commonly used current sensing schemes include resistor current sensing, inductor DCR current sensing, power MOSFET RDSon current sensing, and SenseFET current sensing. Among them, SenseFET current sensing is widely used in switching regulators, such as Intersil's ISL85005 and ISL85014 synchronous buck regulators, due to its high accuracy and negligible power loss. SenseFET current sensing is based on the matched device principle, where the current is divided into the power FET and senseFET, and the magnitude is inversely related to their resistance values. Usually a very high power FET resistance value - senseFET resistance value ratio is used, because the senseFET current is only a small fraction of the power FET current. Therefore, a signal level resistor can be used to sense the current without incurring significant power loss. The first level of cycle-by-cycle current limiting OCP that power supply designers can implement is A) peak current limiting, followed by B) reverse current limiting. Later we will discuss how to implement a second level of protection for sustained fault events.

A. Peak current limit

In a peak CMC buck converter, the switching cycle is initiated by a clock signal. The high-side switch is then turned on and the inductor current begins to ramp up. The inductor current is then sensed and compared to the control signal (V _{COMP ). When the inductor current reaches V COMP} , the high-side switch is turned off and the inductor current decreases until the next switching cycle begins. The peak inductor current is limited to a desired level by clamping V _COMP . Figure 2 shows the current waveforms in normal and current limit operation modes.

Figure 2. Normal and peak current limit operation modes.

Theoretically, once the inductor current reaches the peak current limit threshold, the high-side switch conduction pulse will be terminated immediately to make the inductor current lower than the peak current limit threshold. However, the actual PWM controller usually has a minimum on-time limit. After the clock signal starts a new switching cycle, the high-side switch must remain on for a period of time not less than the minimum on-time before turning off, even if the inductor current has reached the peak current limit threshold.

In the event of a short-circuit fault, the very low output voltage causes the inductor current to decay slowly during the high-side switch off-time. The buck converter must operate at a very small duty cycle to ensure that the inductor current is below the peak current limit threshold. If the control loop requires an on-time less than the minimum on-time, the controller will still keep the high-side switch on for the minimum on-time. As a result, the inductor current continues to increase through each switching cycle and eventually exceeds the programmable peak current limit threshold. Two different methods can be used to prevent this current runaway due to the minimum on-time limitation: implementing a valley current limit circuit, and/or a switching frequency foldback function as a supplementary protection to the peak current limit.

Valley Current Limiting: Provides an additional layer of protection. Valley current limiting can be implemented by sensing the inductor current when the low-side switch is on. If the sensed current exceeds the valley current limit threshold at the end of the switching cycle, the high-side switch will skip the next cycle and remain off until the current decays below the valley current limit threshold. This avoids the current runaway condition due to the minimum on-time discussed earlier. Figure 3 shows an example that explains this protection mechanism.

Figure 3. Peak current limit and valley current limit

Switching frequency foldback: This is another effective solution to eliminate the risk of current runaway due to minimum on-time during a short-circuit fault event. When an overcurrent event is detected, the peak current limit circuit limits the duty cycle, thereby reducing the output voltage. The frequency foldback function reduces the switching frequency when the feedback voltage and/or on-time are below the programmed threshold. Longer on-times can be achieved by reducing the frequency to meet the demanding duty cycle requirements. Current runaway conditions can be avoided by keeping the frequency low enough (so that the demanding on-time is greater than the minimum on-time). Reducing the frequency also results in larger inductor current ripple and lower output current. The frequency will automatically return to normal value after the short-circuit event is removed.

B. Reverse current limitation

In a non-synchronous buck converter with diode rectification, the inductor current is always positive. In contrast, when a synchronous buck converter operates in forced continuous conduction mode (FCCM), the inductor current can flow through the low-side MOSFET in either direction. If the output voltage unexpectedly rises above the output set point, a large negative current will flow from V _OUT to the PHASE node and through the low-side MOSFET to ground. Excessive reverse current can also cause regulator failure.

As discussed above, peak current limiting and valley current limiting can only limit the forward current, but not the reverse current. In this case, an additional reverse current limiting circuit is required. When the reverse current flows through the low-side MOSFET and exceeds the preset reverse current limit threshold, the low-side MOSFET is forced to be turned off.

Secondary OCP Solution

Cycle-by-cycle current limiting provides a rapid first level of protection by limiting the maximum current to a preset level. Switching regulators operating under continuous maximum current conditions experience a significant temperature rise, which may even reach the thermal shutdown threshold in some cases. When this happens, the thermal shutdown protection circuit shuts down the switching regulator to prevent it from being damaged. While the regulator is shutting down, the temperature gradually decreases. After the regulator has cooled sufficiently, it automatically recovers from the thermal shutdown state. In the event of a sustained fault, the regulator cycles between peak current limit and thermal shutdown, which can be detrimental to the long-term reliability of the regulator. At this time, it should be considered to implement two secondary protection mechanisms (hiccup mode or latch-off mode) to eliminate this concern and improve MTBF.

Hiccup mode protection: This protection is usually implemented using a cycle-by-cycle peak current limit and cycle counting circuit. Hiccup mode operation is initiated when an overcurrent event is detected. The cycle-by-cycle limit circuit then reacts to limit the peak current. The cycle counting circuit then counts the switching cycles. After a certain number of consecutive cycles, the switching regulator shuts down for a certain period of time and then attempts to start again. If the overcurrent event has been eliminated, the switching regulator will start up and return to normal operation. Otherwise, it will detect another overcurrent event and shut down again, repeating the previous cycle.

As shown in Figure 4, during a sustained fault condition, the regulator operates for only a small fraction of the hiccup cycle. During hiccup mode, power losses and temperature are much lower. Therefore, power reliability is improved compared to regulators that only employ cycle-by-cycle current limiting.

Figure 4. Hiccup mode OCP under sustained fault condition.

Latch-off mode protection: Like the cycle-by-cycle current limiting scheme, hiccup mode OCP also enables the regulator to restart after the fault is removed. While the auto-recovery feature is popular in many applications, latch-off mode protection is preferred in others, such as in battery-powered systems to prevent battery drain during sustained fault conditions. As shown in Figure 5, latch-off mode protection shuts down the regulator and latches it off when an overcurrent event is detected. Turning on ENABLE or V _IN is required to restart the regulator .

Figure 5. Latch-off mode OCP

Many advanced integrated switching regulators have built-in OCP circuits to protect themselves from excessive current and power loss. Different switching regulators may use different protection schemes. The ISL85003, ISL85005, and ISL85005A synchronous buck regulators from Intersil have internal peak current limit, valley current limit, and reverse current limit functions to provide comprehensive protection. The ISL85009, ISL85012, and ISL85014 synchronous switching regulators also have these current limit functions. In addition, they also provide frequency foldback functions, as well as hiccup mode and latch-off mode protection options to fully protect the switching regulator and improve system reliability.

in conclusion

Power supply designers should make the appropriate selection based on their actual application requirements. Cycle-by-cycle peak current limiting provides fast protection for switching regulators by limiting the inductor peak current, protecting them from excessive current. To avoid the peak current limit from failing due to the minimum on-time limitation, consider using additional valley current limiting and/or frequency foldback functions. Also, don’t forget that reverse current limiting prevents large negative sink currents. As a second level of protection, hiccup mode protection can improve system reliability by reducing power loss and lowering temperature rise. If the automatic recovery feature is not required under sustained fault conditions, latch-off mode protection should be selected.

About the Author

Haifeng Fan is a principal application engineer for power management products at Intersil, a subsidiary of Renesas. He is responsible for new product definition, silicon verification, and customer technical support for Intersil's switching regulator products. Haifeng holds a Ph.D. in Electrical Engineering from Florida State University (Tallahassee), a Master's degree in Electrical Engineering from Zhejiang University, and a Bachelor's degree in Electrical Engineering from Huazhong University of Science and Technology.