“New Challenges” for Chinese Fabs
Latest update time：2020-10-04
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In recent years, TSMC has been developing rapidly in the field of wafer foundry, and the gap between domestic wafer fabs and TSMC in this regard is getting bigger and bigger. But in fact, in addition to the foundry field, the mainland is also being left behind by companies such as Samsung and TSMC in advanced packaging. With the development of Moore's Law, more and more advanced technologies have become the key factors driving the process forward, among which advanced packaging is the first to bear the brunt. Driven by the dual wheels of advanced process and advanced packaging, a "new gap" in mainland China's wafer fabs is gradually fading!
Why do wafer fabs want to attack advanced packaging?
As the technical difficulty and investment scale of the evolution of Moore's Law continue to increase, the semiconductor industry is increasingly dependent on the development of packaging technology. In the past, wafer foundries and packaging plants basically performed their respective duties, but as the terminal's requirements for chips increase, on the one hand, the "memory wall" problem of the processor greatly limits the performance of the processor; on the other hand, as the architecture of high-performance processors becomes more and more complex, the number of transistors increases, and the advanced semiconductor process is expensive, the speed of improving processor yield is far from satisfactory.
The complexity of integrated circuit design and the cost of tape-out are increasing, and the role of microsystem integrated packaging and system assembly is becoming increasingly important. The coordinated design of integrated circuits and packaging has become the key to product success. In this context, the three major chip giants represented by TSMC, Intel and Samsung are actively exploring 3D packaging technology and other advanced packaging technologies.
According to MEMS Consulting, there are two development paths for advanced packaging: 1. Reducing the size to make it close to the chip size, including FC (flip chip, bumping) and wafer-level packaging (WLCSP, fan-in fan-out). 2. Functional development, that is, emphasizing heterogeneous integration and providing multi-functions in system miniaturization, including system-level packaging SiP, 3D packaging, and through silicon vias TSV.
Development History of Integrated Circuit Packaging Technology
Next, let’s take a brief look at the main contents of these major categories of advanced packaging.
First, let's look at wafer-level packaging (WLP). Wafer-level packaging means that most of the process in the packaging process is performed on wafers (large round pieces). It is mainly driven by the demand for smaller package size and height, as well as simplified supply chain and reduced overall cost. There are two types of WLP technology: fan-in and fan-out wafer-level packaging. Among them, fan-out WLP can be divided into die first (Die First) and die last (Die Last) according to the process. The die first process simply means putting the chip on first and then doing the wiring (RDL); the die last means doing the wiring first, and then putting the chip on the unit that has passed the test.
Then there is 2.5D/3D advanced packaging integration. The emerging 2.5D and 3D technologies are expected to be extended to flip chip (FC) and wafer-level packaging (WLP) processes. By using interposers and through silicon via (TSV) technology, multiple chips can be stacked vertically. It is reported that the use of 3D technology can achieve a 40-50 times reduction in size and weight compared to traditional packaging.
Finally, there is the three-dimensional high-density system-level package (SiP/SoP). SiP is a new packaging technology at the highest end of the IC packaging field. It integrates one or more IC chips and passive components in one package, combining the advantages of existing core resources and semiconductor production processes. SiP packaging has also become an important technical solution for achieving high-performance, low-power, miniaturized, heterogeneous process integration, and low-cost system integrated electronic products. The International Technology Roadmap for Semiconductors (ITRS) has made it clear that SiP/SoP will be the main technology for surpassing Moore's Law in the future.
The huge market development scale is also the reason why wafer fabs such as Samsung and TSMC are vigorously developing. According to Yole's latest forecast, from 2018 to 2024, the revenue of the entire semiconductor packaging market will grow at a compound annual growth rate (CAGR) of 5%, while the advanced packaging market will grow at a CAGR of 8.2%, and the market size will grow to US$43.6 billion by 2024. Among various advanced packaging platforms, 3D through silicon via (TSV) and fan-out packaging will grow at rates of 29% and 15%, respectively. Flip-chip packaging, which occupies a major market share in the advanced packaging market, will grow at a CAGR of about 7%. At the same time, fan-in wafer-level packaging (Fan-in WLP), mainly driven by the mobile market, will also grow at a CAGR of 7%.
Advanced Packaging Revenue by Platform, 2014-2024
Samsung, TSMC and other foundries are at the forefront of advanced packaging
In the journey of advanced packaging, TSMC and Samsung are undoubtedly at the forefront of the times. TSMC has taken a leading position in Fan-out and 3D advanced packaging platforms, and its advanced packaging technology has become a mature business and has brought it considerable revenue. Samsung's FO-PLP technology has also been used in its own watches.
TSMC is the first to attach importance to advanced packaging technology, which has become its main difference from Samsung and Intel. Since TSMC introduced CoWoS as a high-end advanced packaging platform for silicon interfaces for heterogeneous integration in 2011, it has pioneered a series of innovations from InFO (and its multiple versions InFO-os, InFO-aip) to SoIC, and then to 3D multi-stack (MUST) system integration technology and 3D MUST-in-MUST (3D-mim fan-out packaging). Among them, CoWoS helped TSMC win high-end HPC chip orders from NVIDIA, AMD, Google, Xilinx, HiSilicon, etc.
According to the latest information on TSMC's official website, they currently have 4 advanced chip packaging and testing factories. After the two new factories are put into production, the number will increase to 6. Foreign media reports also show that TSMC plans to put into production two chip packaging factories in the next two years, which will adopt 3D Fabric advanced packaging technology. During TSMC's 2020 Global Technology Forum and Open Innovation Platform Ecosystem Forum at the end of August, they announced this advanced packaging technology.
Samsung is mainly focusing on panel-level fan-out packaging (FOPLP), and has invested more than $400 million in FOPLP. Samsung's FOPLP is a benchmark for TSMC's InFO-WLP, both of which are packaging technologies for mobile phone chips. On the other hand, Samsung Electronics has developed not only FOPLP but also FOWLP technology to expand its semiconductor packaging technology lineup. In the first half of 2019, it also acquired the semiconductor packaging PLP business of its subsidiary Samsung Electro-Mechanics to continuously strengthen its packaging capabilities.
In October 2019, Samsung announced that it had developed the industry's first 12-layer 3D-TSV (Through Silicon Via) technology. Samsung's new innovation is considered one of the most challenging packaging technologies for mass production of high-performance chips, as it requires extremely high precision to vertically interconnect 12 DRAM chips through a three-dimensional configuration with more than 60,000 TSV holes. The thickness of its package (720㎛) is the same as the current 8-layer high-bandwidth memory (HBM2) product, which is a major advancement in component design. This will help customers release next-generation high-capacity products with higher performance capacity without changing their system configuration design.
Samsung's 3D-TSV (Through Silicon Via) technology
In addition to TSMC and Samsung, Intel also released the 3D packaging technology Foveros, which realizes 3D stacking in logic chips for the first time and heterogeneous integration of different types of chips. The mainland's wafer fabs seem to be relatively low-key in advanced packaging technology. It is understood that among domestic wafer fabs, Wuhan Xinxin is providing 3D IC TSV packaging for image sensors and high-performance applications. In the next few years, advanced packaging will become the focus of competition among the leading semiconductor manufacturers.
Widening the process gap with mainland wafer fabs, jeopardizing the advantage in packaging
TSMC and Samsung's layout in advanced packaging technology has helped them continue to follow Moore's Law and advance to 5nm, 3nm, 2nm and even 1nm processes, which has also made the gap between our mainland wafer factories and them in technology increasingly far. As for 14nm, TSMC has started mass production as early as 2014, and this year it has started mass production of 5nm process, which is expected to account for 8% of the company's revenue. The company expects the 3nm process to be trial-produced next year and mass-produced in the second half of 2022. In contrast, SMIC is six years behind TSMC, and the company announced earlier that it plans to trial-produce TSMC's 7nm chips, which have been in mass production for a long time, in the fourth quarter of this year.
What is even more thought-provoking is whether the entry of these wafer fabs into the advanced packaging field will erode our hard-earned advantages in packaging and testing. As the most competitive link in my country's integrated circuit industry chain, the packaging and testing field has become the leading driving force of my country's semiconductor industry and is driving the rapid development of other links in the semiconductor industry.
Due to the high technical difficulty involved in chip manufacturing, there is a large gap between domestic and foreign levels, and it is difficult to catch up in a short period of time. The technical content of packaging and testing in the back-end of the industrial chain is relatively low. For packaging manufacturers, as long as the chip is produced, it must be packaged. Compared with the manufacturing and design industries, it has less investment, relatively simple technology, and more labor. It is suitable for China's national conditions and is a successful shortcut to the rapid development of the semiconductor industry. Therefore, it has become a key breakthrough area in my country.
In recent years, the domestic integrated circuit industry has flourished, and the packaging and testing industry has also maintained rapid development. From 2004 to the present, my country's semiconductor packaging and testing industry has maintained rapid development, with an annual compound growth rate of 15.8%. According to statistics from the Semiconductor Association, the scale of my country's integrated circuit industry reached 759.13 billion yuan in 2019, of which the market scale of the packaging and testing industry reached 249.45 billion yuan. According to statistics from the Packaging Branch of the China Semiconductor Industry Association, as of the end of 2019, there were 87 packaging and testing companies of a certain scale in my country, including 29 local companies or domestically-controlled companies, with an annual production capacity of 146.4 billion units.
In the global packaging and testing market, Taiwan, China, and the United States occupy the main market share, and their market shares in 2019 are as follows:
According to ChipInsights data, the top ten Chinese domestic packaging and testing foundry companies in 2019 are: Changdian Technology, Tongfu Microelectronics, Huatian Technology, Qizhong Technology, China Resources Packaging and Testing Division, Nengyong Silicon Electronics, Suzhou Jingfang, Chizhou Huayu, Suzhou Keyang, and Liyang Chip. Among the top ten packaging and testing companies, three companies, Changdian Technology, Huatian Technology, and Tongfu Microelectronics, have entered the advanced packaging array.
Through the acquisition of STATS ChipPAC, Changdian Technology has industry-leading high-end semiconductor packaging technology (such as SiP, WL-CSP, FC, eWLB, PiP, PoP and 2.5D/3D packaging under development), as well as mixed-signal/RF integrated circuit testing and resource advantages in important fields such as 5G communications, high-performance computing, consumer, automotive and industrial, and has achieved large-scale mass production, enabling it to provide customized technical solutions for the market and customers.
In the field of 5G mobile terminals, Changdian Technology's high-density system-level packaging SiP technology has cooperated with many international high-end customers to complete the development and mass production of multiple 5G RF modules, and has been applied to a number of high-end 5G mobile terminals. And in the main components of mobile terminals, it has basically achieved full coverage of the required packaging types. The company's high-density AiP solution for mobile phones has been verified and entered the mass production stage; in addition, the company also has a CIS process production line that can be applied to high-performance high-pixel camera modules.
In wafer-level packaging, Changdian Technology has an innovative method for wafer-level manufacturing called the FlexLineTM method, which provides customers with freedom from wafer diameter restrictions, while simplifying the supply chain and significantly reducing costs that cannot be achieved with conventional manufacturing processes. Changdian Technology can provide wafer-level packaging for eWLB (embedded wafer-level ball grid array), eWLCSP (packaged wafer-level chip scale packaging), WLCSP (wafer-level chip scale packaging), IPD (integrated passive devices), ECP (packaged chip package), RFID (radio frequency identification), etc. In addition, Changdian Technology successfully passed the certification of global industry-leading customers in April 2020 and achieved mass production of double-sided packaged SiP products.
According to the first half financial report of 2020 of Changdian Technology, Changdian Technology stated that in the second half of 2020, it will continue to deepen the functional integration of the headquarters, increase investment in research and development of advanced packaging processes and products, actively build a new business platform for design services, and continuously strengthen the core competitiveness of Changdian Technology and implement it at the factory end.
Tianshui Huatian has also been continuously strengthening the research and development of advanced packaging technologies and products in recent years. Through the implementation of scientific and technological innovation projects such as the National Science and Technology Major Project 02 and the continuous research and development of new products, new technologies and new processes, the company has independently developed FC, Bumping, MEMS, MCM (MCP), WLP, SiP, TSV, Fan-Out and many other integrated circuit advanced packaging technologies and products. In the first half of 2020, Huatian Technology's R&D expenses in advanced packaging reached 200 million yuan, a year-on-year increase of 15.41%, accounting for 5.4% of operating income.
In the first half of 2020, Tongfu Microelectronics made breakthroughs in the research and development of 2D and 2.5D packaging technologies. For example, the ultra-large size FCBGA has entered small-batch verification. The research and development of Si Bridge packaging technology has been expanded, and multiple patent families with independent property rights have been deployed. Breakthroughs have been made in the research and development of Low-power DDR and DDP packaging technologies. In addition, various process developments of Fanout packaging technology have been carried out, which are specifically used in CIS, pressure sensors, and photoelectric heart rate sensors. It is planned to complete the proofing of some modules before the end of 2020. It has also built an internationally leading SiP packaging technology design simulation platform and a professional technical team, with the ability to evaluate SiP system-level packaging design and complex packaging design.
Conclusion
Overall, there is still a certain gap between mainland China and international giants in advanced packaging technology. The extension of the supply chain is leading to intensified competition in the packaging and testing industry, and cross-border wafer packaging is becoming a trend. Mainland wafer fabs themselves have a gap in wafer technology, and as major wafer fabs such as Samsung and TSMC gradually move towards advanced packaging, it may become a new "chasm" for mainland wafer fabs.
*Disclaimer: This article is originally written by the author. The content of the article is the author's personal opinion. Semiconductor Industry Observer reprints it only to convey a different point of view. It does not mean that Semiconductor Industry Observer agrees or supports this point of view. If you have any objections, please contact Semiconductor Industry Observer.
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