Popular Science: These are the steps to making chips!

Latest update time：2021-08-31 14:03

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Source: Content from Fujitsu Electronics , thank you.

In semiconductor production plants, wafers are manufactured through extremely fine processing. Thousands of semiconductor devices (chips) of a few millimeters in size are manufactured on a wafer. This manufacturing process is called wafer process, and the process flow is called process flow. Today we will briefly introduce the process flow of semiconductor ICs.

FEOL (Front End of Line: substrate process, the first half of the semiconductor wafer manufacturing process) manufactures components such as transistors on a silicon substrate.

BEOL (Back End of Line: wiring process, the second half of the semiconductor wafer manufacturing process) connects and wires the components manufactured in FEOL to metal materials to form a circuit.

Component Isolation

Transistors are formed near the surface of a silicon wafer.

To ensure that each transistor operates independently, it is necessary to prevent interference with adjacent transistors. Therefore, the formation regions of the transistors are isolated from each other.

Shaft formation

In one chip, n-type MOS transistors and p-type MOS transistors are manufactured separately.

在各自的晶体管制作区域，以适当的浓度的注入各个晶体管所需的杂质（n型MOS： p井，n沟道； p型MOS: n井，p沟道）。另外，可通过追加掺入不同的杂质及不同浓度的剂量來分别制作不同电压/特征的晶体管。

Gate Oxidation and Gate Formation

This is the most important process that determines the performance of transistors.

Because gate oxidation greatly affects the performance and reliability of transistors, it is necessary to form a high-density thin film evenly distributed on the surface of the wafer.

Since the size of the gate formation also has a significant impact on the performance of the transistor, it is necessary to strictly manage the size of the photoresist formation and gate etching. In addition, the gate electrode can be formed by depositing polysilicon using the CVD method.

LDD formation

LDD (Lightly Doped Drain) is formed to avoid the adverse effects of transistor miniaturization (slower operation speed, etc.). LDD is also called extension.

n-type LDD: Add n-type impurities (such as phosphorus, arsenic, etc.) into the n-type MOS region.
p-type LDD: p-type impurities (such as boron, etc.) are added to the p-type MOS region.

Side wall spacing

In order to form the above-mentioned LDD and silicidation of the gate, source, and drain (described below), it is necessary to form an oxide film only on the horizontal wall portion (both ends) of the gate.

Sidewall oxide film: An oxide film is formed on the entire wafer surface.
Sidewall etching: Anisotropic (vertical) etching is performed on the oxide film so that the oxide film remains only on the sidewalls of the gate.

Source and Drain

The source and drain are formed in the n-type MOS and p-type MOS areas respectively. Normally, transistors are bilaterally symmetrical, so their shapes are the same. The direction of the power supply connection determines which end is the source or drain.

p-type source and drain: p-type impurities (such as boron, etc.) are doped into the p-type MOS region.
n-type source and drain: n-type impurities (such as phosphorus, arsenic, etc.) are doped into the n-type MOS region.

Silicide

By silicide (compound with metal) the three electrodes of MOS, namely the gate (polysilicon), source, and drain (silicon), the resistance to the metal wiring layer can be reduced. At the same time, the resistance generated by each electrode can also be reduced.

Silicidation: By chemical etching (self-aligned silicide), only the cobalt film is selectively removed.

Dielectric film

Next comes the wiring process of connecting components such as transistors.

Dielectric film deposition: Formation of thick silicon oxide films, etc. by CVD method.
Dielectric film polishing: In order to make the uneven parts of the crystal surface flat, the dielectric film is polished.

Contact hole

为了将晶体管的三个电极即栅极、源极、漏极透過介质膜之上的金属层相互连接，要对介质膜进行开孔（接触孔）并填充W（钨）。

插件钨填充： 於接触孔内填充钨。
Plug tungsten polishing: Polish the surface to remove excess tungsten so that tungsten remains only inside the contact hole.

Metal-1

形成介质膜，挖沟槽，於沟槽填充Cu（铜）。仅向沟槽内填充Cu（铜）的方式也被称为单镶嵌（single damascene）。

Metal-1 Cu (Copper) Fill: The trench is filled with Cu (Copper) by electroplating.
Metal-1 Cu (copper) polishing: The surface is polished to remove the Cu film (copper film) so that Cu (copper) remains only inside the groove.

Metal-2

形成介质膜，挖孔及沟槽，於孔和沟槽填充Cu（铜）。通过同时向孔及沟槽填充Cu（铜）的方式被称作双镶嵌（dual damascene）。

Metal-2 Cu (copper) filling: Fill the holes and trenches with Cu (copper) by electroplating.
Metal-2 Cu (copper) polishing: Polish the surface to remove the Cu film (copper film) so that Cu (copper) remains only inside the holes and grooves.

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