MIT develops first carbon nanotube mixed-signal integrated circuit

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Image credit: MIT/IEEE

SHARC Attack: MIT's self-healing analog uses RRAM and CNFET technology to create a carbon nanotube op amp in a 4-bit capacitive digital-to-analog converter.

All the amazing carbon nanotube logic we've heard about over the years has a dirty little secret: some of the nanotubes are metallic, not the desired semiconductor type. This small number of bad tubes isn't a big problem for the logic circuits. They add some noise, but nothing that the digital nature of the logic circuits can't handle. The problem has always been on the analog side.

For analog circuits, such stray metallic nanotubes can be like basilisk venom. “A single metal [carbon nanotube] can cause a simple amplifier to completely fail,” Aya G. Amer explained to engineers at the IEEE International Solid-State Circuits Conference in San Francisco last week. Amer and her colleagues in Max Shulaker’s lab at MIT have found a way to solve this problem, creating the first carbon nanotube mixed-signal integrated circuit.

Their solution relies on the 3D integration of carbon nanotube field-effect transistors (CNTFETs) and resistive RAM memory (RRAM). This technology was pioneered by Shulaker while at Stanford University, with the help of H.-S. Philip Wong and Subhasish Mitra. (In July 2016, the three of them co-authored an article in IEEE Spectrum titled "Computing With Carbon Nanotubes," which describes a path to the development of carbon nanotube-based computers.)

The process involves depositing carbon nanotubes on a layer of already produced silicon circuits, processing those carbon nanotubes to form transistors and their interconnects, and then building RRAM on top of that stack. This can't be done with silicon electronic layers, because the process temperatures involved would destroy the metal interconnects. Even stacking pre-processed silicon chips can't match it, because those chips have limited vertical connection capabilities. The method invented by Stanford University/MIT can increase the density of vertical interconnects by thousands of times, thereby improving the bandwidth between layers.

The U.S. Defense Advanced Research Projects Agency (DARPA) was so interested in the technology that it invested $61 million to have SkyWater Technology Foundry in Bloomington, Minnesota, develop the manufacturing process.

Illustration source: MIT

MIT's SHARC approach starts with a carbon nanotube field-effect transistor. The individual metal nanotubes are then separated by breaking up the source electrode. Integrating the RRAM on top of the source electrode creates a circuit that fixes the RRAM resistor in a high-resistance state only where the metal nanotube is located. The field-effect transistor now has only the semiconducting nanotube.

The analog process starts by building the same type of CNTFET needed for logic circuits. That's basically a metal gate buried beneath a channel made of many horizontally aligned carbon nanotubes that run between a source and a drain. At least one of these nanotubes is likely to be metallic; the trick is to isolate it and remove it from any future circuits. To do that, Shulaker's team breaks the source electrode into three parts. Statistically, only one of them will connect to a metal electrode.

To identify which part it was and remove it from the circuit, they integrated an RRAM cell on top of each drain. RRAM stores data in the form of resistance. When current flows in one direction, the resistance increases, and when it flows in the other direction, the resistance decreases. So they applied a voltage across the circuit consisting of the RRAM and the nanotubes. For the two parts with the semiconducting connection, this had no effect; the transistor's gate was not powered, so the current couldn't flow. But for the part hiding the metallic nanotube, the situation was completely different. The metallic nanotube acted as a short across the transistor, and the current flowed out through it and its attached RRAM cell. This caused the resistance of the RRAM cell to jump to such a high value that it effectively cut off the path containing the metallic nanotube. So when the transistor is actually used in the circuit, only the semiconducting pathway is functional.

Amer and Shulaker call the process "Self-Healing Analog Using RRAM and CNFETs" (SHARC); the transistors' own defects can heal themselves. The team used SHARC in the analog portion to build two mixed-signal circuits, a 4-bit digital-to-analog converter and a 4-bit analog-to-digital converter. The latter used 306 CNFETs, making it the largest CMOS carbon nanotube circuit reported to date.

Shulaker said the SHARC technology “fits in really well with a bunch of things we’re doing,” including the SkyWater program. “The DARPA program is about computation, and computation is more than just” digital logic.

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