Exclusive decryption: Why does InFO+16nm beat 14nm?

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Source: Xinyuan

There have been a lot of industry news for several months. The most worrying thing is that Samsung's 14nm is actually mass-produced earlier than our company's 16nm? Mr. Liang is really not a pushover. Frankly speaking, I didn't take these news of verbal battles seriously at first, but then there was the news that the 14nm Exynos processor had been mass-produced, and then it won more than half of Apple's A9 orders, which really made us in the industry anxious all day long. Are we going to go the way of Qualcomm's decline? Is the technological advantage no longer there? This is the pressure in this industry. If there is no technical barrier, we are afraid of being surpassed every day.

It was not until September 14 that the official announcement (Chinanews.com, September 14, "Business Times" report) was made that TSMC had defeated Samsung and exclusively obtained Apple's 16nm A10 processor order. Mass production will begin in March next year, and future revenue and profits are expected to continue to hit record highs. We were really relieved. Suddenly, there was no more news about 14nm. It was strange. (The recent 14nm was jointly developed by GF, IMEC and SMIC, but IMEC is only a patent technology consultant and does not participate in research and development. GF technology is authorized by Samsung. It is estimated that SMIC still has a long way to go~)

Well, not to mention that their yield rate is less than 50%, while our yield rate has exceeded 80%. After reading the news carefully, TSMC's process technology is still 16nm FinFET+, and the main thing is to add the packaging technology InFO (Integrated Fan-Out: integrated fan-out packaging). In the past, I always thought that process technology was the key, but in fact, the company has been planning More than Moore. Looking through the company's 2014 annual report (In addition to the miniaturization of silicon crystal components, TSMC is using advanced packaging technology to perform system miniaturization to increase system transmission bandwidth, reduce power consumption and reduce component size. TSMC continues to expand the application scope of CoWoS technology, from programmable logic gate array (FPGA) applications to network and high-performance computing applications. Among them, high- performance computing applications use 20SoC and 16FF+ technologies in the upper-level die process. At the same time, TSMC has also developed integrated fan-out (Integrated Fan-Out) Fan-Out (InFO) technology supports applications such as mobile and consumer products. Currently verifying 16nm InFO products, it is expected to be mass-produced in 2016; the second generation of InFO technology is also under development to assist the 10nm process to further miniaturize the chip area. ) . Today, let's learn about this InFO technology with everyone. What is it?

Fan-out packaging was first proposed by Intel Mobile in 2009-2010 and was only used for mobile phone baseband chip packaging. Later, in 2013, due to the rise of WLCSP, it was finally abandoned. In the 32nm and 28nm era, WLP packaging was almost still in the RDL (wafer wiring redistribution), Bump (bump flip chip), TSV (silicon through via) and other packaging technologies. Below 28nm, the main packaging technologies are WLCSP, Fan-out WLP, TSV, POP (stacked packaging). The difference between stacked packaging and TSV packaging is that the latter needs to punch holes on the edge of the chip for leads. WLCSP packaging is mainly packaged before the die saw, and then cut after packaging. In this way, the area after packaging is almost the same as the chip, which is suitable for small-size packaging such as sensor and portable. There is also an extremely thin package (bump only 0.5mm) brought by the later developed UBM-free packaging (bump-free metal) technology.

In order to enter the high-end packaging field, TSMC developed the CoWoS packaging technology (Chip on Wafer on Substrate) in 2013, preparing to occupy the 20nm process packaging market at a low cost, focusing on high-complexity memory stacks, which can accommodate 3~4 FPGAs in parallel. However, due to poor yield and cost issues, only FPGA company Xilinx adopted it, and later switched to stacked packaging (PoP), leaving ASE and SPIL to grab the orders. Apple's A7 processor also abandoned CoWoS technology and switched to PoP packaging.

Then came our current InFO. Whether it was CoWoS, PoP technology or through-packaging technology, they all required a substrate, but the cleverness of InFO technology is that it abandoned the substrate, which alone saves 20-30% of the chip cost (the substrate accounts for 50% of the packaging cost). This is just the first temptation, and it is not enough to make Apple, which pursues excellence, extend an olive branch. Of course, money is not the most important thing, the best is yet to come.

First of all, since it abandons the substrate, it needs to adopt wafer chemical processing, so that the interconnect density (Interconnect Density) during connection is higher than the original CSP (Chip Scale Package), so the pin density of the package is high.

Secondly, by abandoning the substrate, the chip thickness is reduced by 0.2mm (20%). The thickness of the traditional PoP stacked package is ~1.2mm, so it is lighter and thinner, and more conducive to heat dissipation and low power consumption.

In addition, the main problem of substrate packaging is the stress matching between the substrate and the chip, which must be alleviated by adding a filler. These problems do not exist without a substrate, and it is an advantage both in terms of stress and pin distribution.

With the above advantages, I don't believe that Apple can't be impressed. It's not surprising that TSMC won the A10 order. In the future, 16nm FF+ with InFO's turnkey technology will occupy the 64-bit application processor, computing processing and low-power market, as well as the x86 and ARM architecture processor market. So the combination of 16nm FF+ and InFO will once again replicate the glory of 28nm HKMG. Let's wait and see.

In addition, let me briefly share with you some of the knowledge I have learned recently about packaging:

1. Since there is fan-out, there must be fan-in?

Yes, the counterpart of Fan-out is Fan-in. The former is called fan-out and the latter is called fan-in. The difference is that Fan-in can only allow the solder ball of the pin to be below the chip surface, while Fan-out allows the pin to exceed the chip through Epoxy Mold Compound, so it can support more pins. It is a compromise between die-level package and wafer-level package. It first makes a die saw and then puts them on the EMC board made of artificial Epoxy.

2. What are 2.5D and 3D packaging?

2.5D mainly refers to two or more chips arranged in parallel on the same substrate, such as CoWoS, which is 3~4 FPGAs arranged in parallel, and another is AMD's HBM (High bandwidth Memory) graphics processor (GPU) technology. 3D IC is a pure vertical stacking packaging technology, mainly represented by TSV and PoP technology.

3. What is the difference between TSMC and ASE’s packaging technology?

TSMC mainly develops wafer-level packaging technology, while ASE mainly focuses on embedded integration technology for substrates, hoping to integrate more bare chips on a single substrate. The two should be very complementary. First, wafer-level packaging is done, and then substrate packaging is done. This should be the future system-level packaging (SiP: System in a Package). It is said that Apple's iPhone 7 will use SiP packaging, so there will be no PCB version. All chips will be packaged in one chip, saving a lot of PCB space for larger capacity batteries and sensor equipment.

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