Raspberry Pi develops its own MCU, why did it choose RISC-V?

Latest update time：2024-09-26

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Source: Content compiled from Raspberry Pi, thank you.

The Hazard 3 RISC-V core in the newly announced RP2350 MCU was designed by Raspberry Pi's own Luke Wren in his spare time - and because they're open source, you can download the design files yourself and start working on the same chip that will eventually be used in millions of devices. As Eben Upton said: "By adding Hazard3 to the RP2350, we aim to give software developers the opportunity to experiment with the RISC-V architecture in a stable, well-supported environment, and promote Hazard3 as a clean, open core suitable for verbatim use in other devices, or as a basis for further development."

“I’ve been doing logic design in my spare time since I was a student. It’s addictive, and I think it’s more accurate to say that I’m a hobbyist doing chip design rather than a chip designer with a hobby! This is an open source processor design that anyone can put into their own chip and run RISC-V code anywhere. You can also run it on an FPGA board, or run a simulator on your own machine. It’s all built using open source tools like yosys, nextpnr, and gtkwave.

“The best way to get started is to get an FPGA board and start programming. Writing RTL [register transfer level] is a little mind-boggling at first—think of it like a C program where all the statements are executed simultaneously, rather than sequentially—but the excitement of seeing your own hardware in action will keep you going. Start with blinking LEDs and move on.

"Hazard3 is 100% my own design. It's a fork of Hazard5, a processor I designed for RISCBoy, my open source competitor for the Game Boy Advance. Hazard5 is a five-stage pipeline, so there are many hazards: data flow, control flow, and structure - a hazard is a 'risk', just like an instruction set.

“Hazard5 is designed to run on the iCE40 FPGA at top frequency, so I can run the RISCBoy graphics core at higher frequencies as well. Hazard3, on the other hand, is a production-grade processor that delivers the highest possible performance in a small footprint and fits within the frequency range I expect to see in a microcontroller design. It’s the production version of Hazard5, with a shorter pipeline, hardware debug, and some of the security and memory protection features that people expect in real systems.

“It took less than a week from forking Hazard5 to getting Hazard3 running CoreMark. From that point to the first RP2350 tapeout took about two years, with development on and off throughout. There is still maintenance going on, and future extensions planned - it will never be "finished", just transitioning from development to a stable release.

“Before starting work on RISCBoy, I had a project called Tarantula, which was an eight-threaded barrel processor that implemented the Armv6-M instruction set, because that was the ISA I was most familiar with at the time, and I wrote some assembly language during a summer internship. I abandoned that project because I realized I could never share it with anyone, and I don’t think I even have that source code anymore.

“That experience changed the way I look at things from that point on. When I decided to build a gaming console from scratch, including the processor, I looked at the instruction sets that were available at the time, and this was around 2018, and there were some interesting ones — the legal restrictions on the Hitachi SuperH had just been relaxed significantly — but RISC-V stood out as the one that I could implement fairly easily.

“The basic instruction set is very concise, and you can add more complexity from a menu of extensions. I can share it with other people, they can actually use it, and I can program with a real production-grade compiler like GCC or LLVM.”

“That was a long time ago, and RISC-V has come a long way, both technically and as a community. Other instruction sets have become more open after RISC-V, but I think the momentum is clear. It’s easy to criticize some of the technical decisions made in the base ISA—do we really need 31 link registers?—but in my opinion, the community is what matters the most.

“I’m excited about RISC-V because it lets you do mad scientist architectural experiments on a clean, standard architecture. If you look at CHERI, which is a really exciting development in embedded security, those guys just wrote a spec and you can just go and implement it — no need to wait for it to come to your desk.”

Improvements of the second MCU

There are a lot of changes from the RP2040 to the RP2350. The main changes are security, higher performance via dual Cortex-M33 processors running at 150MHz, larger memory and new OTP, and lower power modes.

On the RP2040, in a low-power state, with all clocks off, power consumption drops to about 180 microamps. On the RP2350, we can shut off power to most of the chip, reducing power consumption to less than one-tenth, which is useful for low-power applications, such as devices that might spend a long time waiting for input from a sensor.

We went from a regulator to a switcher. A regulator is inherently inefficient under load. So we changed the core power regulator—it's actually a combo device, so it has a small regulator for low-power modes down to 1 mA, when most of the chip is powered down and we're waiting for wakeup. Then when we turn on the core, we switch to a switch-mode power supply, which can deliver up to 200 mA—more than the RP2040, because the chip is larger, so the peak current is higher. The switcher is more efficient than the regulator used on the RP2040.

The PIO is still there; but there are some enhancements. We now have a third PIO block, so four more state machines. We are still using the TSMC 40nm process. Reusing a process you are familiar with saves a lot of time. When you go to a new process node, you have to go get a lot of new IP and learn how to use it.

So sticking to the same flow meant we could reuse some of the IP and knowledge we had done on the RP2040 and RP1 (Raspberry Pi's first in-house chip, used in the Raspberry Pi 5). So we reused the cell libraries, memories, ADCs, PLLs, and USB PHYs from the RP2040.

So there are a lot of things that are the same and we can drop it in fairly easily and then focus on changing the other logic and adding any new IP like OTP or core power regulators. We did review and update parts of the existing design, but there is a lot of new design in the RP2350 and some of the higher level features like power variations or security touch a lot of the silicon and have a broad impact on the design and verification.

Reference Links

https://www.raspberrypi.com/news/risc-v-on-raspberry-pi-pico-2/

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