Challenges of 3D chips

Latest update time：2024-06-29

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Rethinking traditional workflows by shifting left can help solve ongoing problems caused by process and thermal variations.

3D-ICs are a challenge even for designers accustomed to dealing with power and performance trade-offs, but they are considered an inevitable migration path for leading-edge designs due to the computational demands of artificial intelligence and the continued shrinking of digital logic.

3D-ICs are widely seen as a way to continue to push the limits of planar SoCs and to add more heterogeneous devices developed at different process nodes into the same package. But for both planar SoCs and chip components, the laws of physics are insurmountable, and engineers can only use a limited number of tricks before they hit a wall.

Thinner wires in advanced nodes increase resistance, which increases heat. Larger structures, such as 3D-ICs, increase the range of thermal gradients. This is exacerbated by the limited ways to dissipate heat in such structures. Negative effects range from subtle effects such as electromigration to more sudden ones such as chip fires. In addition, as manufacturing process nodes drop into the single-digit nanometer range and then into the angstrom range, it becomes more difficult to control or account for variations, which can lead to serious problems such as increased noise and reduced reliability. All of this requires designers to find an increasingly fragile balance between optimal performance specifications and uncooperative physical realities.

The complexity of 3D-ICs increases the risk of once-theoretical thermal problems, such as spontaneous DRAM refreshes and thermal runaway that can cause devices to shut down. In photonics applications, heat can interfere with communications by changing the wavelength of light.

Figure 1: Temperature distribution of chip and package components. Source: Ansys.

“Heat can also cause timing issues,” said Lang Lin, principal product manager at Ansys. “High temperatures can cause excessive line delays, which slows down the circuit. We hear from foundries that heat is the center of the world.”

Thermal and process variation can be independent issues or multipliers of each other. Regardless, they can cascade and require foresight to resolve. “These issues can be somewhat orthogonal,” said Michael White, senior director of physical verification product management for Calibre Design Solutions at Siemens EDA. “Solving thermal issues has to be done at a more macro level. If I have a thermal issue, the easiest first step is to change the floor plan. If that’s not enough, I can start thinking about things like putting thermal pillars in my active design to draw the heat away from the hot zone. After that, I need to start thinking about where the chip is in the package. In the worst case, if I start out with no options, I have to change the package. I have to put a heat sink on it, and so on. These are all starting with the simplest and lowest-cost options in the overall lifecycle of creating the overall component. If I can shift left, I can figure these issues out early.”

Warping is the primary problem

The biggest challenge facing 3D-IC today is thermally induced warpage. Warpage has gone from being an occasional problem to a persistent issue because highly stacked heterogeneous material configurations cause elevated temperatures and require complex thermal coefficient modeling to avoid yield loss. Additionally, substrates are thinner, which reduces their ability to conduct heat away from the device.

“About a year ago, no one was talking about thermal-induced warpage and stress analysis,” said Melika Roshandell, director of product management at Cadence. “This is starting to come up because of 3D-IC. Designs are becoming more thermally sensitive, and the features are getting smaller and thinner, which has a big impact on warpage. The hot topic at conferences was thermal, but now it’s thermal-induced warpage.”

Lin said the increase in interposer size has also exacerbated the problem. “Today’s 3D IC interposers have become much larger, and can range from 2,000 to 5,000 square millimeters. As a result, the warpage has become so large that it can no longer be ignored. Previously, the warpage was around 5nm, but for large interposers, it can be even higher. The variation in the distance between the two materials can cause mechanical failures, resulting in broken connections between the chips.”

Mechanical stress is another unavoidable consequence of advanced design, adding to the concerns of 3D-IC multiphysics. “The mechanical stress issue is closely tied to the thermal issue,” said John Ferguson, director of product management for Calibre nmDRC applications at Siemens EDA. “As the temperature rises, the wires deform, which changes the mechanical stress. Specifically, the main concern seems to be with the bumps. Are we getting good adhesion and bump definition so that the ohmic contact is formed correctly and adequately? Wafer cracking is another concern, as is warpage in general. If you stack things on top of each other, you have to have both sides planar, or you risk air gaps or other forms of gaps. None of these can be ignored.”

Adding TSVs also becomes an issue. “You’re cutting out big holes and then filling them with other materials,” Ferguson explains. “How you do that without causing some form of warping is not easy. It all depends on how you control the chip process in the beginning to make sure they’re as flat as possible. The next step is to be careful about how you stack things. For example, if we’re talking about stacking one die on top of another, or a second die on top of a wafer, the first step is to make sure you have good planarity methods. That depends on how you fill it, and the manufacturing, the chemical mechanical polishing process, and how well they’re tuned. That can get more challenging when we’re talking about very thin die. If you’re talking about putting individual die next to other die, there are cases where one die is intentionally hanging over another. It’s like a diving board with land on one side and hanging in a pool of water on the other side. That’s definitely where warping can occur.”

The situation has gotten so bad that it’s affecting basic priorities. “SoC designers only care about three things—power, performance and area—but thermal is becoming a fourth. All of the PPA in the past is moving to PPA-T,” said Cadence’s Roshandell. “You’re getting higher performance. That means higher power, and you want to reduce area, so your thermal issues are going to get worse. Thermal is always working against you in all of these areas. You also have to care about signal integrity, power integrity, warpage and other things where thermal is a global issue, with the package and the PCB. You can’t look at your chip in one little corner and your package and PCB in another little corner and say, ‘My package is OK, so I don’t have to worry about anything else.’ You have to consider the entire design when you do thermal analysis. That’s why any engineer has to look at the entire problem and then do thermal analysis. To do that, especially in 3D-IC, you need the tool to have a lot of capacity to be able to read the entire design without simplifying it. If you simplify it, you lose access, and many engineers don’t know where to simplify. As an engineer, you need to remember that this is a global problem, and you need a tool that can analyze it at the earliest stages of the design.”

If thermal analysis isn’t done early enough, problems can arise. Many devices use PVT sensors to detect overheating and then apply thermal throttling as needed. “Thermal sensors dispersed around the chip can monitor local temperatures,” said Siemens’ White. “If the top local temperature is too high, they have the ability to slow down the local clock.”

However, this solution comes at the expense of performance, which makes the devices uncompetitive. “[Thermal throttling] doesn’t solve the problem,” said Marc Swinnen, director of product marketing for Ansys’ semiconductor division. “It detects the problem and then pays to fix it. The cost of not being able to achieve nominal performance because the chip keeps heating up and throttling itself is very high, and it shows that we failed to predict the problem. It showed up, and now we’re paying to reduce power consumption, but that’s not what you want. You want to be able to predict it.”

Shift Left

EDA experts continue to emphasize that the answer to anticipating and reducing problems is to shift left. It is much better to understand and fix potential problems early.

“Before, designers would design the IC, and when everything was done, they would send it to the analysis engineers. But that doesn’t work anymore, especially with 3D-ICs,” Roshandell said. “You have to design and analyze from day one so that if you need to change anything in the design, you can do it right away. Some of the stopgap measures we used to have, like adding fans and heat sinks, don’t work now because the heat transfers so quickly that by the time it gets to the heat sink or liquid cooling, you’re already in thermal runaway. You have to have a risk mitigation plan. The best thing is to know what the risk is from day one so you can find a solution.”

The challenges of changing traditional workflows should not be underestimated. Given human nature, change is often difficult. Designers and companies may not realize the cost and time advantages of changing long-standing workflows. It may take some difficult economic analysis to convince skeptics that, while a shift to the left will be disruptive initially, it will be more cost-effective in the long run.

"Shifting left is all about making designers more efficient," White said. "The way we convince people to adopt this practice is by showing them that while it takes hours to do something today, it can be done in minutes. And after it's done in minutes, it's much cleaner than it would have been using traditional methods. 'See how much faster you can be, and how many fewer bugs you have to debug? Doesn't that sound better?'"

Shifting left can help create more robust, reliable designs, but with the right tools, it can also help the entire design process go faster by reducing the number of iterations. “If you start doing thermal feasibility analysis early, it will let you know where your layout problems are going to be,” White said. “So you can change your layout before you even get it right. If you don’t think about thermal issues until final packaging, and you’ve done the physical layout of every IC, it’s too late.”

reliability

Problems caused by heat and variation are no longer just short-term issues. Reliability is now a major issue in multiple markets, with chips used in critical applications and expected to last much longer. Your best bet for improving reliability is to plan ahead and build in redundancy and resiliency wherever possible.

“A lot of reliability is just basic statistics,” Rob Aitken, distinguished architect in the EDA group at Synopsys, said in an interview. “Assume there’s a probability that a particular event will happen. As we go to lower nodes, there are more devices, which means the probability of something happening is higher. If you have a chip with 50 billion transistors, there are 50 places where a one-in-a-billion event could happen.”

Relying on TSVs to help with thermal management can also increase reliability issues. “One of the biggest reliability failure points in silicon is the vias,” Swinnen said. “These have traditionally been the failure points.”

In short, issues that were once ignored are now prominent problems, and raising awareness is one of the best means of prevention.

in conclusion

Attempts to address heat issues may ultimately push the industry to shift left and rethink activity silos.

“When we visit customers, we end up talking to a lot of different teams that are working in silos,” said Suhail Saif, principal product manager at Ansys. “We advise them that in order to successfully sign off on silicon more efficiently, earlier and at the lowest cost, they need to collaborate. From their perspective, that’s hard to do, but these advanced effects are making them work harder than before. We really need a unified solution across the domains so that they can talk to each other and realize that what they do on one side has a ripple effect on the other side and vice versa. Thermal issues are not the only reason to get together, but they are probably the most serious. It probably has the biggest impact on chip design overall in terms of cost and launch delays. From that perspective, thermal issues are the most important, critical issue that companies cannot ignore if they want to win market share.”

Ultimately, the answers to these questions will most likely come from human collaboration, as well as materials science or physics. “There is a big shift away from silos, from the chip designer all the way to the final product,” Cadence’s Roshandell noted. “People use the same database for analysis, and the chip designer provides the database. We’re seeing a big shift in the industry, with people working together on the same database.”

Reference Links

https://semiengineering.com/design-flow-challenged-by-3d-ic-process-thermal-variation/

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